Printed Circuit Design & Fab - March 2009 - (Page 22) co-desIGn fIGure 2. The ‘374 device, (IC6). fIGure 4. PCB, semi-transparent in 3D to reveal improved routing. fIGure 3. The ‘574 device (IC6). with the ASIC package designer, or better still, you perform both functions, then you can work within that model and improve the package to facilitate better PCB design. This puts the onus back on the ASIC designer, and in this case, it is worth looking at alternative methods for improving connectivity at the silicon level. There is also the weighting of costs and time involved in tradeoffs, such as silicon-thru-via vs. multi-chip-module vs. flipchip or wire bonding techniques. It is important to note that in essence, both the PCB designer and the ASIC designer work with placement, routing and layers of metal. So the tradeoffs can indeed be shared or moved from one domain to the other. In any case, both must be willing to work in a closed loop and to collaborate and share ideas and design data. Therefore, there needs to be mechanisms within the design tools that easily facilitate such transfer (e.g., CSV/Spreadsheet style global editing, smart pasting of design data and collaboration via version controlled design repositories). Today’s design tools have pin-swapping capabilities that go a long way toward solving the problem. These allow the designer to automatically swap gates within a package or pins within each gate where appropriate. This capability spans from simple components, such as decoupling caps and resistor packs, to the most complex BGAs. The idea is to pre-configure components to allow the tool to know which pins are equivalent based on design rules and constraints, then interactively, or in an automated pass, allow it to reduce the routing lengths and crossovers 22 within the rat’s nest. fIGure 5 shows before and after shots of this process. Providing a pin-swapping capability is only half the story. In most cases, the package of the device in question still has a fixedfunction pinout. For example, even tricks that used to apply with memory devices that treated address and data signals as a homogenous group (allowing them to be arbitrarily swapped) are no longer feasible with current memory technologies, due to the fact that address buses are used to access internal configuration registers, requiring a fixed bit-order. Aside from that, there are also banking and interlacing issues. Then there is the other end of the bus, typically a microprocessor of some sort. It is increasingly common for it to be a high pin count BGA. Even with modern packages, in which the core power and grounds are well positioned toward the middle and the IOs around the edges, the tendency of chip manufacturers is to have most GPIOs share a fixed-function peripheral port that you cannot change. Even if the IOs you need are at the edge and easily accessible, you still often need to route around the entire device to get the connections going in the directions you need. State of the Art I am a firm believer in disruptive technology – every now and then something comes along which, at first, may under perform the sustaining technology it competes with, yet offers an irresistible benefit to early adopters who have a need for its flexibility or inherent features. Eventually, with due seasoning, it yields an alternative solution that has no drawbacks. FPGAs are one such technology. Look at the overall growth of FPGA manufacturers and the undeniable performance improvements FPGAs now offer in many applications. Link this to increases in FPGA design starts vs. traditional ASIC design starts, and it is clear that it’s a technology with the power to change how things are done. So what does this have to do with package-PCB co-design, you ask. Apparently, a lot. Of course, one of the technology’s strong points is the fact that the GPIOs are exactly that – general purpose IOs. An FPGA IO pin (and more importantly, the buffer that connects to the pin within the device) is typically capable of supporting in excess of 15 different signaling standards (LVTTL, MARCH 2009 PRINTED CIRCUIT DESIGN & FAB
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