Printed Circuit Design & Fab - March 2009 - (Page 23) co-desIGn Conclusion Here is where the future looks very bright. Because this technology exists today in CPLDs and FPGAs, many of the patents held regarding configurable IOs are now nearing the end of life. Between the next three to five years, we are likely to see many additional chip vendors augmenting their devices with programmable IO pin capabilities and programmable routing resources similar to what is available today in FPGAs. Imagine an 8051 derivative with a JTAG debug port that also allows the user to completely define their own custom pinout that suits their product. Imagine an ARM microcontroller that has reconfigurable IO with crossbar switches and user-defined SERDES capability, where YOU can decide which pins will be clocks and which will be I2C IOs. As ECAD tool and silicon IO technology advances, we can expect to attain the optimal pinout for every design, without sacrificing product performance or the designer’s time. PCD&F fIGure 5. Before and after pin swap. CMOS, STL, LVDS, HSTL, LVPECL). In addition, there are usually no fixed-function (meaning fixed in hard silicon) peripheral cores directly linked to a given IO bond pad. Instead, the IOs sit alongside vast multiplexors and on-die routing resources that allow the FPGA designer to specify which pins to use for their given purpose. Bear in mind, a trade-off exists between fitting the design on the target FPGA and obtaining timing closure versus allowing the PCB layout to entirely govern the pin assignments. But to a great extent, the PCB designer can have a say in how the pin assignments are made, reducing PCB routing time, improving PCB signal integrity and potentially reducing the number of required layers. What this means is that with FPGAs, we have the freedom to swap pins and IO banks to improve the layout, but the design tool is then used to push the new net connections back to the schematic and forward to the FPGA constraints file – all through a salubrious ECO process. BenJamIn Jordan is a field applications engineer with Altium Inc; ben.jorden@altium.com. “We are extremely pleased with how our quality has improved since converting to Taiyo solder mask. We wish we had switched years ago.” EXCEPTION PCB A proud Taiyo Partner. www.exceptionpcb.com ➤ (LEFT TO RIGHT) STEVE CAMPISI, Taiyo America JOHN FIX, Taiyo America GORDON HOLDEN, Managing Director LIAM LYNCH, Lamar PHIL CRABB, Quality Engineer ROB HUNTER, Quality Manager DISTRIBUTED BY: 2675 Antler Drive • Carson City, NV 89701-1451 • Phone [775] 885-9959 • Fax [775] 885-9972 • www.taiyo-america.com MARCH 2009 CircuiTree Ad DEC08_vFINAL.indd 1 PRINTED CIRCUIT DESIGN & FAB 2/17/09 9:32:45 AM 23 http://www.exceptionpcb.com http://www.exceptionpcb.com http://www.taiyo-america.com http://www.taiyo-america.com
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