Printed Circuit Design & Fab - March 2009 - (Page 25) dfm taBLe 2. DfM enhancements in design to improve manufacturability. Item ReSuLt fROm eNhANcemeNt The balancing of copper on the surface of the design will improve the distribution of plating (in the pattern-plating process), preventing areas of overplating due to the isolation of features. This improvement enables the manufacturer to control the plated hole diameters to tolerances and reduce plating heights, which impact solder mask coverage. Warpage, that might result from uneven plated areas side-to-side, can also be eliminated or reduced. As annular rings decrease due to tighter design specifications, the probability of defects occurring due to registration/ annular ring failures increases. The addition of Teardropping increases the pad-to-trace junction size, improving the reliability of the connection and improving product yields. Innerlayer shorts result from several factors, among them the proximity of circuitry to other circuitry. The occurrence of shorts can be correlated to the running length of the circuitry versus the running length at some minimum spacing between circuitry (at the process capability of the operation). Reducing the total distance at minimum spacing will reduce the probability of shorts, resulting in improved yields. Innerlayer shorts result from several factors, among them the proximity of circuitry to other circuitry. The occurrence of shorts can be correlated to the running length of the circuitry versus the running length at some minimum spacing between circuitry (at the process capability of the operation). Reducing the total distance at minimum spacing will reduce the probability of shorts, resulting in improved yields. The occurrence of opens can be correlated to the running length of the circuitry versus the running length at minimum track width (at the process capability of the operation). Reducing the total distance at minimum track width will reduce the probability of opens, resulting in improved yields. Copper balancing Teardropping Removal of nonfunctional pads on innerlayers fIGure 1. Where do you conduct the Manufacturing Compliance Audit? Optimization of track-tofeature spacing Track width optimization ity. This means that design for manufacturing verification must become a standard part of the design process– it’s YOUR job. In order to reduce the costs of building the designs and to meet the tightened time-to-production schedules, fabrication and assembly compliance checks must be made during placement, critical routing, power supply design and manufacturing documentation. The entire design process must integrate the requirements of the fabricator and assembler before launching a product into manufacturing. Design systems lay out circuits to defined rules (DRC); however, the systems adhering to these rules usually fail to represent the full extend of what constitutes manufacturability (manufacturing compliance). The purpose of reviewing the data package, in addition to reviewing the documented design constraints, is to confirm that the product can be produced at the manufacturing site and to the expected manufacturing yields. The analysis of the data describing the circuitry of MARCH 2009 the PCB to the manufacturing facility’s production capabilities is critical to the success of the product. fIGure 2 shows that the typical DRC is a subset of manufacturing compliance rules (MCR), representing the difference between CAD, DRC and the full manufacturing compliance rules. DRC is an ideal process for design, but MRC continually validates the designs’ manufacturability. Figure 2 illustrates that, like an onion, there are layers to manufacturing compliance. The example highlights this complexity: the inset via is a very useful HDI design feature but not all CAD systems will permit this feature, so the MRC must be sensitive to weather this is a designed feature or, an error in placement or routing. Once created, MCR files represent software specification that can be shared between design and manufacturing engineering as they collaborate throughout the entire product supply chain. Using the MCR inside the EDA environment, a designer can graphically see these manufacturing ranges, as seen in fIGure 3. Partnering with the fabricator and assembler to understand these rules files will ensure that the manufacturing knowledge is built into the layout process. As described in the MCR, each analysis category must be driven by its own set of acceptability parameters to define the limits of yield compromise: SEVERE: Unacceptable according to specifications MODERATE: In the borderline zone, requiring judgment from a skilled engineer WARNING: Acceptable but in a gray zone considered to be not best practice OK: Acceptable according to specifications With hundreds of discrete analysis functions and a range of different designs, interconnect technologies and manufacturing process options, an infrastructure is required to maintain all the variable rules and constraint parameters that have an impact on manufacturing yield, quality and cost. The MCR allows the engineer to capture all physical specifications and manufacturability constraints on demand. In the same way that Signal Integrity (SI) Analysis and Power Integrity (PI) Analysis can be driven by constraints captured during schematic input and permanently stored as part of the design file, these Manufacturing Compliances Constraints can be stored PRINTED CIRCUIT DESIGN & FAB 25
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