Printed Circuit Design & Fab - June 2008 - (Page 27)

common ground for realistic signal integrity analysis. FiGurE 2 shows an eye diagram measurement obtained from a parallel bit error rate tester (parBERT) when a 800 mV p-p differential signal is transmitted through the device under test (DUT) at 2.125 Gbps using a PRBS7 bit pattern. The DUT includes a driver test card attached to a back plane through an AIRMAX connector, with a receiver test card attached through a GBX connector. SMA cables from the parBERT generator are attached to the driver test card SMA connectors. The SMA connectors on the receiver test card feed into a sampling scope for capturing the eye waveform. It can be seen from Figure 2 that the eye height is approximately 440 mV. The measured voltage waveforms, relative to ground, on individual pins of the differential pair at the receiver side are shown in FiGurE 3. Differential receivers effectively subtract these two signals to get the final waveform. It can be noted that the sum of the two voltages are not zero, which indicates the presence of common mode voltage. This common mode voltage appearing between the pins of the differential pair at the receiver side is plotted in FiGurE 4. It can be seen that the peak-to-peak magnitude of the common mode voltage is around 170 mV, which will greatly affect the signal integrity of the multi-board system by generating ground-to-ground noise. FiGurE 5 shows the common mode noise appearing between the ground pins of the AIRMAX connector on the driver test card and the back plane. The magnitude of the common mode noise is about 205 mV for the 2.125 Gbps input. This ground-to-ground noise will severely affect the signal integrity of the design and cannot be captured using conventional signal integrity analysis, as discussed in a later section. Therefore, it can be concluded that the impedance discontinuity at the board interfaces, which is conventionally ignored, must be considered for realistic signal integrity analysis. Modeling of PCB Connectors for Inductance Extraction The common mode noise that appears between the ground pins in different boards will depend on the common mode current and the loop inductance of the signal lines at the connector. Therefore, accurate analysis and successful design of PCBs with multiple boards connected to a main board need to factor in the loop inductance contributed by the connectors, which depends on the actual current return paths. Since the common mode current flowing through the signal pin returns through the ground pins, the separation of the signal pin from the ground pins and their relative positioning plays an important role in determining the loop inductance. Finding the pin configuration that minimizes inductance is very important for PCB signal integrity. In this paper, Partial Element Equivalent Circuit (PEEC) method, and magnetic energy conservation method are employed to efficiently analyze inductance. The PeeC Model. The model of Figure 1 is implemented in IBM’s PEEC solver, PowerPEEC. Small lengths of microstrip lines with a characteristic impedance of 50 Ω are used to obtain the inductance as seen by the microstrip lines. The actual dimensions of the AIRMAX connector’s pins are used for modeling the DUT. Different possible configurations of the ground pins are considered for estimating the YOU’RE ! FiGurE 3. Individual output voltage measured at the two differential pins showing the existence of common mode voltage between the pins. FiGurE 4. Waveform of common mode voltage (170 mV p-p) appearing in between the differential probes of Figure 3. JUNE 2008 ! FiGurE 5. Common mode noise (205 mV p-p) voltage appearing between the ground pins in two planes. printEd circuit dESign & fAB 27 http://www.photoplot.com

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Printed Circuit Design & Fab - June 2008

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