Printed Circuit Design & Fab - June 2008 - (Page 35) board images while performing the initial inspection. The results of the initial inspection are an acceptance or rejection of the stored parameters of the acquired data. An image from a golden board is then used as a reference to compare it with images of inspected boards. Cameras scan the device under test (DUT) for catastrophic failures or missing components and quality defects, also known as manufacturing processes defects. These defects include fillet size, the shape of solder joints, and component skew, among others. The design of AOI cameras plays an important role in boosting their effectiveness. The objective here is to place the camera at an angle so that it can achieve maximum light collection for component inspection. This allows the camera to capture as much area as possible to apply a wider field of coverage to an inspected device. AOI can be applied at various stages of the manufacturing process, including bare board inspection, and can be used to verify the inner layer stack up, lamination tolerances, and registration of layers at the bare board manufacturing level. At the PCB assembly level, AOI can perform solder joint inspection at pre- and post-reflow stages. At pre-reflow, AOI inspects for the placement accuracy of the components that the pick-and-place machine has dispensed. At post-reflow, it can check for accurate component placement after the board is processed through a reflow oven. In the bare board application, AOI can be used to verify trace and space width and violations, as well as inspect for FiGurE 2. AOI in debug and fine tuning mode verifies the component against the similar component in the database parts library. excessive or insufficient copper removal during or after the etching process. AOI also can inspect for trace shorts, cuts, jumps, and other defects in the manufacturing process. Therefore, it is important for the PCB fabricator and EMS provider to use AOI inspection at various stages of the process. AOI can also serve as a process validation indicator and reduce the amount of rework and touch up at the end of the assembly process, increasing the process yield in a PCB fabrication operation. GerberStasis Film To Software Archiving Services GerberStasis services were designed to provide flexible cost options to companies seeking to develop a comprehensive back up plan for their legacy film libraries. While scanning films to TIF or JPEG files creates a software image, it also increases the cost to convert that image to a usable Gerber file for future production. Precision Images, LLC offers a strategic approach to legacy archiving that allows the customer to select the backup version based on the probability of the PCB being manufactured in the future. For as little as $5.00 per layer you can achieve the following benefits: • • • • • • Dimensional and feature size accuracy. PCB industry’s standard data format. Photoplot images for continued reverse engineering on any scanning system. Import to Gerber CAD/CAM systems as reference layers. Import to many PCB design programs as reference layers. Convert to DXF for import into AutoCAD as reference. Precision Images, LLC • 727 544-0201 • www.precision-images.biz JUNE 2008 printEd circuit dESign & fAB 35 http://www.precision-images.biz http://www.precision-images.biz
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - June 2008 Printed Circuit Design & Fab - June 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Final Finish Forum DFA/DFT Signal Integrity From the Field DFA Fab Basics Drill Off the Shelf Marketplace Ad Index BGA Bulletin Printed Circuit Design & Fab - June 2008 Printed Circuit Design & Fab - June 2008 - Printed Circuit Design & Fab - June 2008 (Page Cover1) Printed Circuit Design & Fab - June 2008 - Printed Circuit Design & Fab - June 2008 (Page Cover2) Printed Circuit Design & Fab - June 2008 - Printed Circuit Design & Fab - June 2008 (Page 1) Printed Circuit Design & Fab - June 2008 - Contents (Page 2) Printed Circuit Design & Fab - June 2008 - Contents (Page 3) Printed Circuit Design & Fab - June 2008 - Our Line (Page 4) Printed Circuit Design & Fab - June 2008 - Our Line (Page 5) Printed Circuit Design & Fab - June 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - June 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - June 2008 - Around the World (Page 8) Printed Circuit Design & Fab - June 2008 - Around the World (Page 9) Printed Circuit Design & Fab - June 2008 - Around the World (Page 10) Printed Circuit Design & Fab - June 2008 - Around the World (Page 11) Printed Circuit Design & Fab - June 2008 - Happenings (Page 12) Printed Circuit Design & Fab - June 2008 - Happenings (Page 13) Printed Circuit Design & Fab - June 2008 - ROI (Page 14) Printed Circuit Design & Fab - June 2008 - ROI (Page 15) Printed Circuit Design & Fab - June 2008 - Tip Jar (Page 16) Printed Circuit Design & Fab - June 2008 - Tip Jar (Page 17) Printed Circuit Design & Fab - June 2008 - Interconnect Strategies (Page 18) Printed Circuit Design & Fab - June 2008 - Interconnect Strategies (Page 19) Printed Circuit Design & Fab - June 2008 - Final Finish Forum (Page 20) Printed Circuit Design & Fab - June 2008 - Final Finish Forum (Page 21) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 22) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 23) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 24) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 25) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 26) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 27) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 28) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 29) Printed Circuit Design & Fab - June 2008 - From the Field (Page 30) Printed Circuit Design & Fab - June 2008 - From the Field (Page 31) Printed Circuit Design & Fab - June 2008 - From the Field (Page 32) Printed Circuit Design & Fab - June 2008 - From the Field (Page 33) Printed Circuit Design & Fab - June 2008 - DFA (Page 34) Printed Circuit Design & Fab - June 2008 - DFA (Page 35) Printed Circuit Design & Fab - June 2008 - DFA (Page 36) Printed Circuit Design & Fab - June 2008 - DFA (Page 37) Printed Circuit Design & Fab - June 2008 - Fab Basics (Page 38) Printed Circuit Design & Fab - June 2008 - Fab Basics (Page 39) Printed Circuit Design & Fab - June 2008 - Drill (Page 40) Printed Circuit Design & Fab - June 2008 - Drill (Page 41) Printed Circuit Design & Fab - June 2008 - Drill (Page 42) Printed Circuit Design & Fab - June 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - June 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - June 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - June 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - June 2008 - Ad Index (Page 47) Printed Circuit Design & Fab - June 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - June 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - June 2008 - BGA Bulletin (Page Cover4)
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