Printed Circuit Design & Fab - June 2008 - (Page 38) FAB BaSicS When a good Doe goes Bad Estimate the time constant of a process prior to conducting the DOE to prevent erroneous results. by J LEE PARKER When designing a DOE it is important to quantify the duration of the transient portion of the process before you begin. This parameter will evolve from the analysis as a time constant for the transient phase of the process. This parameter can then be used after starting the process to numerically define the appropriate time delay before starting the DOE. Knowing the magnitude of the time constant is also important in controlling the quality of the process. Without knowing the time constant, compensating adjustments are made during the transient portion of the process and the output of! these will vary. The transient time is often a great deal larger than anticipated by conventional wisdom and can negatively impact the DOE outcome. The two primary approaches used by fabrication engineers to resolve processing issues are either to employ their basic understanding of the process mechanism, or to use a DOE that is a statistical analysis method. In the case of a DOE, there are two basic assumptions. First, that all of the primary independent variables are included in the experiment, and second, that the process is not time dependent. If either of these underlying postulates are not the case, then the DOE will most likely be a failure. In the past, most of us have experienced DOEs that generated results that were unrepeatable or erroneous. Given the pressures of the situation, we often resort to intuition to resolve technical problems. The purpose of this article is to analytically quantify one of the potential pitfalls mentioned above, which will corrupt the results of even the most carefully planned and executed DOE. In particular, many DOEs involve processes that, at least initially, are not stationary and a startup transient exists. Typical examples are wet chemistry processes. We all realize that initially such a process may be transient, and we may attempt to compensate for this by allowing the process to “settle down” before collecting any 38 data. Often the marker that defines the “settling point” is something as significant as a subtle change in color. Investigative Model The process that will serve as the focus of interest for this analysis is the single chamber inline counter flow processor as shown in FiGurE 1. Processors of this design are used as etchers, developers, surface preparation, etc. This example is Work Flow Spray heads f V f FiGurE 1. In a process chamber, the working fluid is pumped up and through spray nozzles and allowed to collect in the sump. !!!!"#$%&'!()! ! printEd circuit dESign & fAB JUNE 2008
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - June 2008 Printed Circuit Design & Fab - June 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Final Finish Forum DFA/DFT Signal Integrity From the Field DFA Fab Basics Drill Off the Shelf Marketplace Ad Index BGA Bulletin Printed Circuit Design & Fab - June 2008 Printed Circuit Design & Fab - June 2008 - Printed Circuit Design & Fab - June 2008 (Page Cover1) Printed Circuit Design & Fab - June 2008 - Printed Circuit Design & Fab - June 2008 (Page Cover2) Printed Circuit Design & Fab - June 2008 - Printed Circuit Design & Fab - June 2008 (Page 1) Printed Circuit Design & Fab - June 2008 - Contents (Page 2) Printed Circuit Design & Fab - June 2008 - Contents (Page 3) Printed Circuit Design & Fab - June 2008 - Our Line (Page 4) Printed Circuit Design & Fab - June 2008 - Our Line (Page 5) Printed Circuit Design & Fab - June 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - June 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - June 2008 - Around the World (Page 8) Printed Circuit Design & Fab - June 2008 - Around the World (Page 9) Printed Circuit Design & Fab - June 2008 - Around the World (Page 10) Printed Circuit Design & Fab - June 2008 - Around the World (Page 11) Printed Circuit Design & Fab - June 2008 - Happenings (Page 12) Printed Circuit Design & Fab - June 2008 - Happenings (Page 13) Printed Circuit Design & Fab - June 2008 - ROI (Page 14) Printed Circuit Design & Fab - June 2008 - ROI (Page 15) Printed Circuit Design & Fab - June 2008 - Tip Jar (Page 16) Printed Circuit Design & Fab - June 2008 - Tip Jar (Page 17) Printed Circuit Design & Fab - June 2008 - Interconnect Strategies (Page 18) Printed Circuit Design & Fab - June 2008 - Interconnect Strategies (Page 19) Printed Circuit Design & Fab - June 2008 - Final Finish Forum (Page 20) Printed Circuit Design & Fab - June 2008 - Final Finish Forum (Page 21) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 22) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 23) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 24) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 25) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 26) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 27) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 28) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 29) Printed Circuit Design & Fab - June 2008 - From the Field (Page 30) Printed Circuit Design & Fab - June 2008 - From the Field (Page 31) Printed Circuit Design & Fab - June 2008 - From the Field (Page 32) Printed Circuit Design & Fab - June 2008 - From the Field (Page 33) Printed Circuit Design & Fab - June 2008 - DFA (Page 34) Printed Circuit Design & Fab - June 2008 - DFA (Page 35) Printed Circuit Design & Fab - June 2008 - DFA (Page 36) Printed Circuit Design & Fab - June 2008 - DFA (Page 37) Printed Circuit Design & Fab - June 2008 - Fab Basics (Page 38) Printed Circuit Design & Fab - June 2008 - Fab Basics (Page 39) Printed Circuit Design & Fab - June 2008 - Drill (Page 40) Printed Circuit Design & Fab - June 2008 - Drill (Page 41) Printed Circuit Design & Fab - June 2008 - Drill (Page 42) Printed Circuit Design & Fab - June 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - June 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - June 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - June 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - June 2008 - Ad Index (Page 47) Printed Circuit Design & Fab - June 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - June 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - June 2008 - BGA Bulletin (Page Cover4)
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