Printed Circuit Design & Fab - June 2008 - (Page 39) ! 1 (1 f i f ) exp( t / ) (1) 1 T ! 1 Ts 1 (2) FiGurE 2. The holding tank levels of contaminate increases over time. selected since it is one of the simplest wet chemistry processes in the industry. In this case, a working fluid is circulated at a rate, designated f, into and out of a holding tank. The fluid is pumped through the spray heads and onto the work piece (panel) where it removes the unwanted (and potentially troublesome) materials from the panel. The working fluid then drains from the panel and back into the holding tank bringing with it the unwanted superfluous material. This process increases the concentration of the superfluous material in the holding tank, consequently reducing the removal rate of this unwanted contaminate. It is assumed that the removal rate is inversely proportional to the concentration of the contaminate material. From this point forward we will draw on the analysis developed in the reference. FiGurE 3. The value of time constant as a function of independent variables. Ts f V AE m Equation 3 (3) Analysis One of the primary dependent variables characterizing the DOE would be the concentration of superfluous contamiEquations nate material introduced into the holding tank. That is, the ratio of the superfluous material to the volume of the tank, and it is a major variable influencing the dissolution Equations rate of the working fluid. At any time ‘t’, the concentrai tion ‘β’ is: 1 (1 ) exp( t / ) f f (1) (1) 1 (1 f i f ) exp( t / ) Equation 1 where: βƒ is the stationary concentration of the working fluid βi is the initial concentration of the working fluid 1 Equations is the time constant of the transient portion of the process 1 T timeTs 1 t is Analytical1relationships for the solution concentration and the time1 constant in terms of the independent processing T Ts 1 i variables are found in the reference/ . We will first focus upon 1 (1 ) exp( t 1 ) the time constant. The exponential behavior of such a process f f is depicted in FiGurE 2. It is normally assumed that the process is stationary after fV Ttime constants (when the transient is 98% complete). s four AE m Obviously, it is imperative that the time constant be deterfV mined. Ts (2) (2) (1) rEFErEncE where: V is the volume of holding tank ρ is the density of the superfluous material being removed from panel A is the active area over the holding tank Em is the maximum removal rate of superfluous material from panel. FiGurE 3 shows the value of the time constant as a function of these independent variables. It is not unreasonable to expect the time constant to range between 0.2 and 0.4 hours. The implication here is that the process does not become stationary until 0.8 to 1.6 hours (four time constants), and before starting the characterization of the stationary process (by a DOE), this much time should be allowed to elapse after startup or the validity of the evaluation will be in doubt. Similar observations can be made concerning processing production grade product immediately after startup. For instance, since the concentration of superfluous material in the working fluid is increasing, the removal rate is decreasing, and consequently, the break point occurs later in the process. This analysis has been carried out using a very simple process to illustrate the point. It is important that the physics of the process be understood before attempting to optimize it by carrying out a DOE. In particular, the time constant of the process should be estimated either by an analytical calculation or a series of measurements prior to conducting the classical DOE. pcd&f 1. “A Mathematical Model for an Inline Counter Flow Processor” J. Lee , Parker, Ph. D., IPC Apex, April 2008. (3) AE m 1 1 T Ts 1 (3) Equation (2) 2 J. lEE ParkEr is president of JLP Consultants and can be reached at leep001@msn.com. printEd circuit dESign & fAB 39 where: T is the turnover time of the holding tank and JUNE 2008
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - June 2008 Printed Circuit Design & Fab - June 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies Final Finish Forum DFA/DFT Signal Integrity From the Field DFA Fab Basics Drill Off the Shelf Marketplace Ad Index BGA Bulletin Printed Circuit Design & Fab - June 2008 Printed Circuit Design & Fab - June 2008 - Printed Circuit Design & Fab - June 2008 (Page Cover1) Printed Circuit Design & Fab - June 2008 - Printed Circuit Design & Fab - June 2008 (Page Cover2) Printed Circuit Design & Fab - June 2008 - Printed Circuit Design & Fab - June 2008 (Page 1) Printed Circuit Design & Fab - June 2008 - Contents (Page 2) Printed Circuit Design & Fab - June 2008 - Contents (Page 3) Printed Circuit Design & Fab - June 2008 - Our Line (Page 4) Printed Circuit Design & Fab - June 2008 - Our Line (Page 5) Printed Circuit Design & Fab - June 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - June 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - June 2008 - Around the World (Page 8) Printed Circuit Design & Fab - June 2008 - Around the World (Page 9) Printed Circuit Design & Fab - June 2008 - Around the World (Page 10) Printed Circuit Design & Fab - June 2008 - Around the World (Page 11) Printed Circuit Design & Fab - June 2008 - Happenings (Page 12) Printed Circuit Design & Fab - June 2008 - Happenings (Page 13) Printed Circuit Design & Fab - June 2008 - ROI (Page 14) Printed Circuit Design & Fab - June 2008 - ROI (Page 15) Printed Circuit Design & Fab - June 2008 - Tip Jar (Page 16) Printed Circuit Design & Fab - June 2008 - Tip Jar (Page 17) Printed Circuit Design & Fab - June 2008 - Interconnect Strategies (Page 18) Printed Circuit Design & Fab - June 2008 - Interconnect Strategies (Page 19) Printed Circuit Design & Fab - June 2008 - Final Finish Forum (Page 20) Printed Circuit Design & Fab - June 2008 - Final Finish Forum (Page 21) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 22) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 23) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 24) Printed Circuit Design & Fab - June 2008 - DFA/DFT (Page 25) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 26) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 27) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 28) Printed Circuit Design & Fab - June 2008 - Signal Integrity (Page 29) Printed Circuit Design & Fab - June 2008 - From the Field (Page 30) Printed Circuit Design & Fab - June 2008 - From the Field (Page 31) Printed Circuit Design & Fab - June 2008 - From the Field (Page 32) Printed Circuit Design & Fab - June 2008 - From the Field (Page 33) Printed Circuit Design & Fab - June 2008 - DFA (Page 34) Printed Circuit Design & Fab - June 2008 - DFA (Page 35) Printed Circuit Design & Fab - June 2008 - DFA (Page 36) Printed Circuit Design & Fab - June 2008 - DFA (Page 37) Printed Circuit Design & Fab - June 2008 - Fab Basics (Page 38) Printed Circuit Design & Fab - June 2008 - Fab Basics (Page 39) Printed Circuit Design & Fab - June 2008 - Drill (Page 40) Printed Circuit Design & Fab - June 2008 - Drill (Page 41) Printed Circuit Design & Fab - June 2008 - Drill (Page 42) Printed Circuit Design & Fab - June 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - June 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - June 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - June 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - June 2008 - Ad Index (Page 47) Printed Circuit Design & Fab - June 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - June 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - June 2008 - BGA Bulletin (Page Cover4)
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