Printed Circuit Design & Fab - June 2008 - (Page 48)

BGA Fanout Patterns, Part 4 Creating effective fanout patterns for microvias in an hDI stackup. HDI MICROVIA FANOUTs for laser drilled micro-via stackups use the same principles as mechanically drilled blind and buried vias. The variety of cHArlES stackups and smallpfEil er via sizes provide for tighter shifted column and row patterns, improved route density and greater flexibility in assigning routes to buildup layers than does standard laminated cores. When using HDI, the blind microvias allow for greater route density, and therefore potentially fewer total layers required for routing. Of course, the number of layers accessible by the micro-vias will significantly affect the overall route density. The fanout patterns analyzed in this context will be for the following types of HDI construction: 1+N+1 = Type II (Layer 1:2 microvias with buried vias in a laminated core) 2+N+2 = Type III (Layer 1:2, 2 to 3 microvias with buried vias in a laminated core) they can be further compacted to gain additional route space. In FiGurE 1, the 1:2 microvias are aligned in columns to maximize route density (12% improvement over shifted blind vias, 36% improvement over quadrant dog-bone through vias.) It is easy to see how route density can be increased when using via-in-pad methods. If the vias are shifted inside the pads as shown in FiGurE 2, you can open up additional room for the escape traces. If only one layer is available for the escape traces, as is the case with a 1+N+1 stackup that has a ground plane on the surface layer, then it is important to use a shifted via pattern that is allows for aligned microvias around the BGA perimeter. This will allow space for the power and ground to extend through the board using additional buried and blind vias. Layer 1:2, 2 to 3 microvias (2+N+2) Again, assuming that Layer 1 will be a ground plane, then the fanouts need to be patterned to maximize the Layer 2 and Layer 3 route density. FiGurE 3 and FiGurE 4 show how effective the general principle of aligning vias works to open additional route space on inner layers. Figure 3 shows that the shifting of vias not only provides additional route density, but it also opens space for uninterrupted ground fill. Also note how nicely the ground via fits, and the how the copper fill and clearance around it provides for ease of manufacturing. The thermal relief ties are also rotated off the 45-degree center, to maximize the connectivity and make room for the nearby fanout via. In Figure 4, note the significant space for routes after shifting the vias. In this case, the traces are routed as single-ended nets, however, if the nets were differential pairs, there would be plenty of room to route three sets of differential pairs between the aligned vias. Of course, practical applications such as these may vary depending on design rules. The power (orange) and ground (green) vias are paired because both the 1:2 vias, but also the 2:3 vias can be seen on Layer 2. Observe as well the wide-open space for traces on Layer 3, where the buried via starts.Results may vary depending on actual design rules. In the above examples, the trace widths are 0.1mm/4th and the via pad size is 0.254mm/10th. Effective fanout patterns can significantly increase route density. Designs with through vias under BGAs have limited options, but by using laminated blind vias, route density can be increased 24%, and using HDI micro-vias allows a 36% increase in route density. Continued on p. 47 Layer 1:2 microvias (1+N+1) If Layer 1 is used for a ground plane and not for routing, then the fanouts need to be patterned to maximize Layer 2 route density. The same patterns described in the previous month’s article for blind vias can be used for microvias, however, since the microvias are smaller, ! FiGurE 3. Layer 1 with 1:2 microvias for all ball pads. FiGurE 1. Microvias aligned. 48 ! FiGurE 2. Microvia pattern using viain-pad method. ! ! FiGurE 4. Layer 2 escape traces and microvias, Layer 3 buried vias. JUNE 2008 printEd circuit dESign & fAB

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Printed Circuit Design & Fab - June 2008

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