Printed Circuit Design & Fab - August 2008 - (Page 30)

co-dESiGn is worth it. But if the cost increase is very large, the choice lies between performing a more accurate analysis or taking a risk that could lead to project delays or product field problems. The transient active current simulation can reveal more inclusive waveform characteristics that would otherwise be missed by this technique and others. analysis. An example of such a transient. The analysis indicated that an expensive modification to the package design would be needed to handle this current spike. However, when presented with this data, the IC circuit designers came up with a plan to move the timing of the blocks to reduce the total dI/dt of the event. The ability to do this type of simulation depends on the cooperative effort between the designers on both sides of the interface in question. As devices and systems stretch performance capabilities, design practices must change accordingly. Today, very few vendors are willing or even capable of providing the information required for transient active current analysis. In the case, where only the step current spec is available, the evaluation of the PDS may end at that point. This brings up a difficult decision point for the system designer – whether the step current analysis indicates sufficient margin, all errors considered – or whether to put more pressure on the part supplier for information. In the long term, it may be necessary to improve the power sink and power distribution specification with some new standards. Our research has yielded at least one technique for expediting the compliance process for PDS design. need to be able to specify the level of highfrequency noise that will feedback to the board PDS. Better yet, they should strive to provide models that end users can use in their system simulations. Conclusion This paper presents a review of our experience dealing with the problems delivering power reliably within a large computer system. Many smaller system manufacturers do not have to deal with these problems, at least not on a large scale, but advances in technology threaten to make them much more commonplace. While many new software tools have been designed to deal with these problems, there is still a good deal of confusion surrounding how they are to be used and how to correlate simulation data through the system hierarchy. Facing some of these large-system problems at an earlier time, we were obliged to develop our own tools and techniques to deliver products successfully. At this time, we are seeing a lot of industry-wide concern that power delivery problems are getting out of hand, but from our viewpoint, this need not be the case. A host of powerful tools are coming of age, but we feel that the knowledge gap at this time is the lack of a unified approach to the analysis of the PDS. We have attempted to propose such an approach, including basic, essential and advanced methods of measuring performance of the PDS. We have also proposed methods for linking the simulations of different levels of the PDS, at the same time simplifying and expediting the task. These methods suggest a framework for advanced PDS modeling, similar to the IBIS standard that has been generally accepted for I/O simulations. pcd&f Ed. Note: Part 1 of this article was published in July. The complete article can be found at pcdandf.com/cms/cms/ content/view/4909/95/. Transient Active Current Although the current step and killer virus methods go a long way toward characterizing the package and system response, there is no assurance that the worst-case simulation is represented or that the PDS is optimized to the circuit. It is usually the only approach early on in the design project, since more precise information is not available. The hardest part of the transient active simulation can be obtaining the proper current draw information. We have had the luxury of being in contact with IC designers who can run IC simulations with ideal power supplies and measure the current drawn from those supplies. The designers usually give us data in large piecewise-linear listings, representing the current drawn by “blocks” of circuits. In return, they want to know what the PDS voltage looks like for those blocks under this current draw. The IC is divided into several irregular shaped blocks, meaning that the model of the IC power load must be constructed with a number of load models arranged in a pattern that accurately represents the map of the die. In a similar fashion, the current map of a packaged part on a PCB may need to be divided into a grid of models to represent the footprint of the package. When the model is simulated, the geometrical effects of the current paths are automatically evaluated, as are the interactions with adjacent blocks or packages. In one instance, a particularly current hungry block was found to be “borrowing” charge from capacitance in an adjacent block by way of the package planes. This kind of information is very difficult to obtain by any other means. Given that the current draw information is available in detail and that the detailed 3-D model is in place, a close examination of all aspects of the voltages in the system is possible. Certain events on the IC can cause high current transients that were unforeseen in the initial 30 Backward Leakage of High-Frequency Noise Increasing high-frequency noise in ICs can produce problems for inter-die communication and generate radio frequency interference (RFI). The higher switching speed of new generation ICs is a fact of life, but it puts a strain on the co-design of the entire PDS. The highest frequency components can only be bypassed by ondie capacitance, which puts a heavy load on the IC power designer. The package and board bypass capacitors typically have too much ESL to effectively short out the gigahertz and higher frequencies. Using proper design practices, the inductance of package planes and vias can be used to advantage to block high frequencies. The use of embedded passives has also been employed for this purpose. Electronic band gap structures have been employed for this purpose as well, but more esoteric techniques such as plane shaping and slotting have also been effective in reducing resonances, power noise and EMI in PCB designs. Vendors of ICs davE Quint is a master engineer at hP working on IC fabrication, package design, signal integrity and power delivery system integrity and can be reached at dave.quint@ hp.com. charlES kEEn is an analog engineer for hP and can be reached at charles.keen@hp.com. printEd circuit dEsign & faB AUGUST 2008 http://pcdandf.com/cms/content/view/4909/95/

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - August 2008

Printed Circuit Design & Fab - July 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Software Performance Interconnect Strategies Final Finish Forum Product Development Challenges in a Global Market Innovative Modeling Supports Co-Design of the Power Supply Chain, Part 2 Low-Loss Fluoropolymer Copper Clad Laminate Qualifying PCBs Outsourced in Asia Copper Plating and Microvia Fill for Advanced PCBs Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - August 2008

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