Printed Circuit Design & Fab - August 2008 - (Page 42)

PlatinG A wide variety of system design features that further enhance via filling performance may be incorporated in VIL plating equipment. These include the use of insoluble anodes and engineered fluid delivery devices such as eductors or nozzles designed to create impinging flow on panel surfaces. Insoluble anodes improve plating uniformity by presenting a more stable anode profile over time than copper anodes. Coupled with increased solution flow, insoluble anodes also allow the use of higher operating current densities. Considering all the different factors that influence process selection for copper via filling, vertical in-line plating equipment offers a very attractive combination of excellent process capability with attractive equipment cost. There are a number of commercially available vertical in-line plating systems. fiGurES 3 and 4 show systems that are commercially available from Process Automation International Ltd (PAL) Hong Kong and Applied Equipment Ltd. Taiwan. depending on a number of considerations, including via dimensions, board layout, customer requirements and equipment capabilities. Proper control of pretreatment processes also plays an important role in achieving good via filling yield. A typical process sequence uses acid cleaner, micro-etching and acid dip steps to make sure the copper substrate is clean (free of contamination and surface oxidation) and properly prepared for the subsequent copper plating step. Summary Vertical in-line plating systems offer an attractive alternative for high-volume PCB manufacturing with features particularly suited to copper microvia filling. In conjunction with more capable equipment, copper via filling electrolytes are also evolving to provide more capable and consistent performance. This combination of VIL equipment and chemistry offers end-users a cost-effective, highly capable and production-proven process for HDI substrate microvia filling. pcd&f Factors Affecting Microvia Filling The key process factors affecting via filling performance, other than process chemistry formulation and bath composition, are solution flow, current density and pretreatment process. While lower levels of solution flow will generally improve via filling performance, particularly of large (100 µm or above) vias, this improvement comes at the price of increased risk of improperly filled small (75 µm or less) diameter vias. Improper fill may manifest itself as defects ranging from seams within the plated deposit to completely voided vias. The consequence of this behavior is that equipment parameters must be optimized to achieve acceptable levels of fill and plating quality for the specific applications being run. The effects of current density are somewhat less complex, as lower current density will both enhance via filling performance and also produce product with lower levels of improperly filled vias. However, the impact of current density is strongest at the very early stages of via filling. Once vias have partially filled, higher current densities can be applied without adverse effects. While the simplest way to operate a plating process might be to run a single set of flow and current density parameters, use of a more complex operating scheme, incorporating variable flow and current density at different times in the plating cycle, can yield better via filling quality at higher overall production throughput. Although such complex plating cycles can, in principle, be applied to vertical batch processes, their implementation in VIL equipment is much easier. The flow and current density settings in individual modules can be set at different levels to create the desired profile of these two parameters with plating time. Specifically, flow would be greatest and current density the lowest in the initial modules, switching toward lower flows and higher current densities in later modules. The detailed parameter setting will vary 42 brucE chEn is assistant engineering manager RD&e – Rohm and haas electronic Materials Taiwan Ltd. he may be contacted by email at: hcchen@rohmhaas.com. BGA Bulletin, continued from p. 48 NSeW. Using a NSEW pattern in which layer bias is completely ignored will use the least number of layers for escaping the BGA. Layer Biased. A general layer-biased approach that ignores netline direction will generally require more layers to escape the BGA, but it should enable more effective autorouting. Netline Direction. Routing escapes with a layer bias and orienting them in the direction of the netline uses the most layers but enables the most direct routing. This method is also most effective if an autorouter is used. It is important to remember that the BGA fanout pattern has the greatest impact on route density. An effective fanout pattern will, as a result of increased route density, enable the fewest number of layers and give you the flexibility to choose an escape route method that satisfies your other constraints. pcd&f charlES PfEil is an engineering director for Mentor Graphics, Systems Design Division. email: charles_pfeil@mentor. com. you can obtain a copy of Charles’ new book, “BGA Breakouts & Routing” at www.mentor.com/go/bga AUGUST 2008 printEd circuit dEsign & faB http://www.mentor.com/go/bga

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - August 2008

Printed Circuit Design & Fab - July 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Software Performance Interconnect Strategies Final Finish Forum Product Development Challenges in a Global Market Innovative Modeling Supports Co-Design of the Power Supply Chain, Part 2 Low-Loss Fluoropolymer Copper Clad Laminate Qualifying PCBs Outsourced in Asia Copper Plating and Microvia Fill for Advanced PCBs Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - August 2008

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