Printed Circuit Design & Fab - August 2008 - (Page 48)

BGA Layer-Biased escapes Effective fanout patterns increase route density and enable the fewest number of layers while meeting other design constraints. 1500 pins), it is unlikely that it will be routed without using an autorouter. Manual routing over 10,000 connections simply takes too long. Autorouters continue to be enhanced with the goal of emulating interactive routing results, and the use of autorouters, especially for large boards, makes sense. Using an autorouter in these conditions makes sense; however, autorouters are biased and NSEW escapes are not compatible with layer-biased autorouting. If the escape routes are NSEW, the layer-biased routing will block the routing of those escapes in the opposite bias (fiGurE 3). The style of the layer-biased escape routes in Figure 2 are similar to NSEW escapes in Figure 1 in that the direction of the escape route is independent of the netline direction. Ignoring the direction of the netline is appropriate when just getting the traces out of the BGA array is a problem. Once you get out of the array, then you can direct the routing to the target pins using the open space of the board. When the design rules are conservative, escaping the large BGAs becomes the primary contributor to layer count, and just routing out of the array becomes a larger problem than ensuring the initial direction of the routes matches the direction of the netline. be even more effective if the escapes are in the direction of the netline towards the target – especially if there are large buses. Granted, this may increase the number of layers required to escape the BGA; however, as long as the total number of layers is reasonable in terms of cost and reliability, escaping in the direction of the netline is a good method. In fiGurE 4, the connections in the center of the BGA were escaped in the direction of the netline. The completed routing will be more direct when using this method. In summary, three approaches to escape routing can be applied alone or in combination. Each one has its own advantages. Each design is a unique challenge and determining the most effective method for escaping the BGA depends on design rules, signal and power integrity concerns andthe pin pitch of the BGA. Continued on p. 42 WheN DISCUSSING BReAKoUTS on a BGA, the traditional pattern for the escape routes is what I call North South East West (NSEW), as shown cHarlEs in fiGurE 1, with pfEil the traces escaping from the center of the BGA in all four directions on each layer. This pattern is effective when there are few layers, numerous busses and the desire to manually route without a layer bias. Layer-Biased Escapes A layer-biased approach orients the escapes in the same direction as the bias for the layer. Layer biasing utilizes the principle that escape routes on a horizontally biased layer will be horizontal and escapes on a vertically biased layer will be vertical – as shown in fiGurE 2. Layer 2 has a horizontal bias, and Layer 3 has a vertical bias. In this example, a 1-3 microvia was used on the outer eight rows of the BGA, and through-vias are used in the center. These fanouts were aligned in a manner that maximizes the route density as described in the BGA fanout articles over the last four issues of this magazine. There are situations where a layerbiased approach can be more effective than NSEW. If the design is very large (more than 16 BGAs, each with over Netline Direction Using the layer-biased approach, can fiGurE 3. NSeW escapes blocked. ! fiGurE 1. NSeW breakouts. 48 ! fiGurE 2. Layer biased breakouts. ! fiGurE 4. Layer biased with netline direction considered. AUGUST 2008 ! printEd circuit dEsign & faB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - August 2008

Printed Circuit Design & Fab - July 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Software Performance Interconnect Strategies Final Finish Forum Product Development Challenges in a Global Market Innovative Modeling Supports Co-Design of the Power Supply Chain, Part 2 Low-Loss Fluoropolymer Copper Clad Laminate Qualifying PCBs Outsourced in Asia Copper Plating and Microvia Fill for Advanced PCBs Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - August 2008

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