Printed Circuit Design & Fab - August 2008 - (Page W13)

3- DAY TECH N I CA L CONF E RE NCE PROGRA M WEDNESDAY, SEPT. 17 9 am – 11 am NEW! W5 – Breaking New Ground in PCB RF Design Speakers: Per Viklund and Loy Dz’Souza, Mentor Graphics Designing mixed analog-digital PCBs requires considerably more effort than single-signal PCBs. Crosstalk between signals must be avoided, and analog circuits can be susceptible to the EMI generated by high-speed digital circuits. Stepping beyond that and including RF signals with analog and digital on the same PCB induces even more issues that must be properly dealt with. With the increasing number of wireless products inﬁltrating the market, PCB designs that place all three types of circuits on a single board are becoming more and more common. This two-hour workshop identiﬁes many of the issues, and presents solutions and design considerations for mixed-RF/analog/digital PCB designs. between PCBs and semiconductor technology (wafer-level integration) is greater than one order of magnitude in interconnection density capability, although the development of ﬁne-pitch substrates and assembly technology has narrowed the gap somewhat. All viable efforts are being used in ﬁlling this void utilizing uncased ICs (ﬂip-chips and incorporating more than one die or more than one part in the assembly process. This half-day seminar provides a comparison of different commonly used technologies, including ﬂip-chip, chip-size, wafer-level and 3-D array package methodologies detailed in a new publication, IPC-7094. It considers the effect of bare die or die-size components in an uncased or minimally cased format, and the impact on current component characteristics, and reviews the appropriate PCB design guidelines to ensure efﬁcient assembly processing. The focus of the IPC document is to provide useful and practical information to those who are mounting bare die or die-size array components or who are considering the adoption of miniature IC package technology. 1:30 pm – 5 pm NEW! S7 – Power System Design on High-Speed PCBs Speaker: Rick Hartley, L-3 Communication, Avionics Systems The power distribution section of a PCB is the foundation around which all things work in the circuit. If this is not designed correctly, the entire circuit is at risk from noise, to say nothing of the severely increased possibilities for EMI. Low impedance in the power bus across the range of harmonic frequencies of a digital circuit is critical. This half-day seminar will cover the major components of the power bus, the power distribution path, medium- and high-frequency decoupling concerns, the importance of IC pin assignments, placement of decoupling, real performance of capacitors (verses myth), how much decoupling is enough, why use one value of capacitor, anti-resonant peaks, the importance and performance of power/ground planes and the importance of board stack. 9 am – 11 am W6 – Designing for Asian Fabrication Speaker: Happy Holden, Mentor Graphics If there were ever a time to have a full understanding of DFM, then having your boards built in China is that time! This workshop will highlight the issues, choices, alternatives and conditions that designers need to consider in order to make a PCB manufacturable in Asia, especially China. Attendees will learn how to determine if a fabricator is capable of handling an order; how to use IPC-9151 capability benchmarking to select fabricators; when to control impedance; plating, ﬁnishes and thickness distribution; mechanical and image tolerances; materials, multilayer stackup and hole plugging; thieving, plating concerns and why plating thickness varies; calculations vs. 2-D ﬁeld solvers; and much more. 11 am – 1 pm NEW! W8 – Probing Signal Integrity – Measuring High-Speed Circuits Speaker: Robert Easson, Analytical Edge Engineers and technicians traditionally rely on oscilloscopes and logic analyzers to test digital PCBs. With many IC output drivers now having sub-nanosecond rise times, routine oscilloscope measurements to test digital PCBs may be inadequate to resolve high-speed design issues. Other measurement instruments such as the time domain reﬂectometer (TDR) and vector network analyzer (VNA) may provide more meaningful information. In addition, Gb/s serial transmission brings a new set of measurement requirements such as BER (bit error ratio), ISI (inter-symbol interference) and eye patterns. This two-hour workshop looks at what needs to be measured on a PCB (signals and system paths) and how well they can be measured (as a function of time or frequency). Beginning with a review of TDR, VNA and oscilloscope measurements (explained in simple terms of voltage, current and reﬂection), attendees will gain insight into the beneﬁts and limitations of each technique from a high-speed design standpoint. Attendees will also learn how to assess the measurement bandwidths required for accurate signal measurement, how circuit probes degrade measurements, and how to choose what techniques may work best in speciﬁc situations. BER, ISI and S-parameter measurements are included in this tutorial 1:30 pm – 5 pm S8 – Vias and Their Effects on HighSpeed Signals Speaker: Robert Hanson, Americom Seminars Vias are much more than holes; they can have a profound effect on your digital signal. This half-day seminar will cover the mechanical properties of vias – from drilling and plating, to lamination, electrolysis and electroplating. Attendees will learn about capacitance and inductance of vias; return current and its relation to vias; through-hole, blind, buried and microvias; methods for drilling; aspect ratios; and cost tradeoffs. Discussion will focus on whether vias and autorouters are HDI compatible, via discontinuity and via resonance concerns, capacitance and inductance of vias (through-hole, blind, buried), eliminating reﬂections of vias, and return current and intelligent via placement. 9 am – 11 am NEW! W7 – Panel Session: IC-PackagePCB Co-Design Strategies Panelists: TBD The electronics industry is poised on the brink of major changes in the way we approach system design. SoC devices and SiPs need design teams comprised of members from all disciplines; chip, package and board designers need to cooperate to bring a successful design to completion. Concurrent co-design methodologies, supported by collaborative software systems, are making way for fundamental changes that will impact the basic roles of engineer and circuit designer in the future. Through a number of case study examples, this two-hour panel session will highlight the current changes in electronic system design that will impact your design future. 1:30 pm – 5 pm NEW! S9 – Making the Most of Your Design Time Speaker: Susy Webb, Fairﬁeld Industries Layout time is often one of the last things considered in the project cycle, so designers need to manage their time wisely to get the job done. This half-day seminar will discuss ways to do that from many angles of the design. We will discuss: streamlining the input and output processes; fully utilizing the software including using macros and scripts; optimizing the design preparation and layout; and making the checking, saving and ECO processes more manageable. 1:30 pm – 3:30 pm NEW! W9 – Panel Session: HalogenFree Update Speakers: TBD Why halogen-free? The question was raised more than 20 years ago and the debate continues. What are the advantages to eliminating halogen from the electronics supply chain? Is the proposal based on science? Or a knee-jerk response to a misguided ideal? With the rapid changes in the regulatory positions on speciﬁc bromine materials, the requirement to move toward supposedly “greener” halogen-free laminates is faltering. No law exists to push acceptance of these halogen-free materials forward and it seems clear that speciﬁc efforts to push for a removal of bromine from laminate materials is losing ground. We have invited experts in the area of halogen-free electronics to present current global positions on the topic. Expect an informative discussion and spirited debate at this two-hour panel session. 9 am – 12:30 pm S6 – Microelectronics Design, Chipon-Board, Flip Chip and 3-D Package Technologies Speaker: Vern Solberg, consultant As new generations of electronics products emerge, they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies. This movement is occurring at all levels: the IC, the IC package, the module, the hybrid, and the PCB, which ties all the systems together. Interconnection density and methodology become the measure of successfully managing performance. The gap Early Bird Discount Deadline | Re g i ste r b y Au g u st 1 9 a n d sa v e u p to $ 1 0 0 !

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - August 2008

Printed Circuit Design & Fab - July 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Software Performance Interconnect Strategies Final Finish Forum Product Development Challenges in a Global Market Innovative Modeling Supports Co-Design of the Power Supply Chain, Part 2 Low-Loss Fluoropolymer Copper Clad Laminate Qualifying PCBs Outsourced in Asia Copper Plating and Microvia Fill for Advanced PCBs Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - August 2008

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