Printed Circuit Design & Fab - September 2008 - (Page 26)

DESIGN baSicS a systematic approach to incReasinG LayeR counT Increasing layer count requires an organized design approach to avoid re-spins and reduce time-to-market. by JOHN PELOSO There are many issues associated with adding layers to a printed circuit board. First and foremost, the addition of layers can be the result of a customer requirement. In many case, consumer driven electronics forces designers to increase the complexity and layer count in the design. To expedite the delivery of next generation products, designers are including more and more proven reference designs. Some of the most common reference designs include peripheral interfaces (such as USB, PCI, PCI-X, PCI-E, etc.) and memory interfaces (DDR, DDR2, etc.). These designs will typically be constructed on a predetermined stack-up. These reference designs may also include drivers and/or receivers from programmable devices such as FPGAs. These devices are becoming a more popular choice as the central hub for two specific reasons: space reduction and proven signal integrity. Miniaturization is another common reason why designers are pressured into adding layers to the design. Here again, consumer electronics drive the need for functional equivalents in smaller packages. This is apparent with MP3 players, cellular telephones and a host of other consumer goods. Because of this, components that incorporate greater functionality are used to replace older circuitry. These new devices are often high-pin BGA packages, which require additional layers to fan-out and to get the huge number of signals routed from the BGA package onto the PCB. Signal integrity is also a common item of concern for this type of interconnect. The switching speeds on these devices are very fast–typically under 2 ns. Implementing designs with these types of characteristics requires exact placement and termination strategies. Smaller overall design footprints also increase the need to account for crosstalk and electromagnetic coupling between traces. Along with the increased design speeds, impedance matching has now become another important concern. Addressing These Intertwined Challenges The BGA fan-out. Designs that include BGA devices have the unique requirement to add additional layers to account for fanout & escape patterns. As designers face these types of challenges, investment in adopting a PCB tool (FiGurE 1) that supports rules for individual decals & components is a must. ! FiGurE 1. BGA fanout often dictates that an increased number of layers be included in the design. 26 ! FiGurE 2. Proper trace termination is essential with very fast switching signals. SEPTEMBER 2008 printEd CirCuit dESign & fAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - September 2008

Printed Circuit Design & Fab - August 2008 Contents Our Line Market Watch Around the World Happenings ROI Positive Plating Off the Shelf Marketplace Ad Index EMC for the Real World Final Finish Forum Design for Green: Laminates A Systematic Approach to Increasing Layer Count The NTI $100 Million Club Printable Nanocomposites BGA Bulletin

Printed Circuit Design & Fab - September 2008

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