Printed Circuit Design & Fab - September 2008 - (Page 48)

BGA The 0.8mm Pin Pitch BGAs, Part 1 Microvias reduce layer count when routing high pin count BGAs. ALTHoUGH I AM unaware of any BGA with a pinpitch of 0.8 mm and over 1500 pins, the day will come when they replace the large CHArlES 1mm devices. The pfEil FPGA companies who are approaching 2000 pins with 1-mm pin-pitch are correctly concerned about the transition to 0.8 mm. Exceeding 2000 pins with 1-mm pin-pitch results in a very large BGA that is not only more expensive to manufacture, but also more difficult to attach to the board due to potential warping of either the device or the board. The FPGA customers want increased functionality (resulting in more pins), yet they have no experience routing such a large and dense device. Using the principles described previously for 1-mm BGAs, this three-article series will explore fanout and breakout solutions for routing the large 0.8-mm devices. This first article explores the use of through vias with FR-4. For the purpose of testing, a footprint for a Virtex-5 with 1760 pins at 1mm pitch was converted to 0.8-mm pitch. There are 1227 I/Os that need to be escaped. The rest of the pins are power and ground. Testing continued by applying fanout patterns using the North East South West (NSEW) method and applied breakout patterns for three different via configurations. Test 1: Through Vias. The first test used only through-vias with the intent to demonstrate the number of layers required for such a method so it could be compared to the other more efficient solutions. The design rules, as shown in FiGurE 1, for the first test are the same 48 as used in the 1-mm pitch tests from the previous articles, except the ball pads are a little smaller due to the smaller pin-diameter and pin-pitch. Test 1: Fanout Patterns. A common question question from designers is, "How can I reduce the layer count?” If you are fortunate enough to work with the ASIC or FPGA designers, you can potentially have them organize all the perimeter pins so they are used for I/Os. This can reduce the layer count simply because more of the I/Os can be routed on the first signal layer. Another method that applies to all BGAs that use through vias is to push the fanouts out and away from the perimeter of the ball pads. This technique allows for an extra two rows of I/Os to be routed on the first signal layer. In most cases, this will result in a reduction of one signal layer for escaping the BGA. One signal layer may not sound like much, but depending on your situation it may actually mean you can reduce the stackup by two signal layers just because the symmetry of the stackup require two layers to be added together. FiGurE 2 illustrates pushing the fanouts out and away from the perimeter. The intent was to move the vias far enough out so that three traces could be routed between them on the diagonal. In the center of the BGA, use a simple matrix dog-bone pattern that opens up the route channels in the center rows and columns. Test 1: Breakout Results. When using the through via only, it took seven routing layers to accomplish the NSEW breakout. If the perimeter vias where not pushed out, it would have taken eight layers. If you work on every escape trace, packing them in with the maximum pain (PCB designers will know what I am talking about), then you may even be able to reduce the total layer count for escaping this 1760 pin (1227 I/ Os) device to six layers. Unfortunately there isn’t much you can do to reduce layer count when using through via fanouts on these 0.8-mm BGAs. However, you can eliminate one to two layers with the above techniques. Using microvias will allow this BGA to be escaped in only five or even reduced further to three signal layers depending on the stackup and via methodology. These other methods will be explored in the next two articles of this series. pCd&f charlES PFEil is an engineering director for Mentor Graphics, Systems Design Division. Email: charles_pfeil@ mentor.com. At www.mentor.com/go/ bga you can obtain a copy of Charles’ new book, “BGA Breakouts & Routing. ” Figure 1. Design rules for through vias. Figure 1. Design rules for through through vias. FiGurE 1. Design rules for vias. FiGurE 2. Pushing fanouts away from the perimeter. SEPTEMBER 2008 printEd CirCuit dESign & fAB http://www.mentor.com/go/bga http://www.mentor.com/go/bga

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - September 2008

Printed Circuit Design & Fab - August 2008 Contents Our Line Market Watch Around the World Happenings ROI Positive Plating Off the Shelf Marketplace Ad Index EMC for the Real World Final Finish Forum Design for Green: Laminates A Systematic Approach to Increasing Layer Count The NTI $100 Million Club Printable Nanocomposites BGA Bulletin

Printed Circuit Design & Fab - September 2008

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