Printed Circuit Design & Fab - October 2008 - (Page 18)

PCb Stack-up Analysis and Design, Part 1 Small, higher-density PCBs cost less to fabricate than high layer count boards, but closely spaced traces can result in crosstalk issues. tHE tERM “StACk-uP” refers to the arrangement and the types of layers in a multilayer board. The design of a PCB stack-up involves ascertaining the number of signal layers1 needed to route the board and the ground/power planes demanded for adequate power distribution. It is recommended that the layers are arranged dr. ABE so that each high-speed trace is referenced (ABBAS) riAzi to a continuous plane2. Furthermore, it is desirable for the stack-up to include parallel (adjacent) power and ground layers for enhancing capacitive decoupling and reducing EMI, and the PCB stack-up will strongly influence impedance of a power distribution system (PDS). Prepreg (also called B-stage) consists of a glass cloth coated with resin (epoxy) that has not been fully cured. A prepreg layer is applied between two internal layers (or cores) of a multilayer PCB to function as glue through the lamination process. A core is a thin piece of dielectric (cured fiberglass-epoxy resin) with copper foil bonded on both sides. The term laminate also refers to a composition of two sheets of copper foil laminated to a piece of woven glass cloth saturated with resin and fully cured. The thickness of the copper foil is expressed in ounces3 that represent the weight of copper per square foot of surface area. Three common thicknesses are 0.5 ounce, 1.0 ounce and 2.0 ounce. Copper foil of 1.0 ounce (~1.4 mils) thickness is produced by plating to a thickness sufficient to equal one ounce of copper distributed over a one-square-foot area. Use of 1.0 ounce copper foil is quite popular in PCB fabrication; however, 0.5 ounce ground/power planes can be sufficient for all high-speed PCBs with exception of those that demand very high power levels. Copper foil that is categorized as 1.0 ounce foil has a thickness of approximately 1.2 mils and 0.5 ounce foil has a thickness of 0.6 mils in the completed circuit board because of of anticipated copper losses that result from the chemical processes used in the manufacturing process. The thickness of plane ground and power layers adds to the total PCB thickness. Standard PCB thickness values4 include 39 mils, 62 mils, 93 mils and 125 mils, but other board thicknesses (for instance 100 mils) can be also obtained. Stack-up parameters such as spacing between layers, substrate dielectric materials and trace dimensions need to be selected properly in order to meet the board impedance and crosstalk requirements. Several stack-up features can be illustrated by considering a four-layer PCB, as depicted by FiGurE 1. Ground and power planes perform multiple functions, one of which is to distribute power to various devices, but they also furnish a means for achieving controlled impedance transmis18 sion lines. The plane layers can appreciably diminish noise and radiation levels. At frequencies5 exceeding 10 MHz or 15 MHz, incorporation of power and ground layers, such as a multilayer stack-up as opposed to a two-layer board is recommended. In Figure 1, the layer order from top to bottom is Sig, Gnd, Pwr and Sig, which implies that the outer layers are formed by the signal layers, and the inner layers are the ground and power. Another possibility is to have ground and power plane layers as outer layers (Gnd, Sig, Sig, Pwr). This scheme can provide greater shielding6, but it is accompanied by several drawbacks. For example, the planes need to be cut to allow component placement, and rework on the board becomes more difficult. The stack-up depicted by Figure 1 is a common arrangement for a four-layer PCB; the parallel power and ground planes can furnish interplane capacitance3 which is important in the stack-up design of high-speed PCBs. The capacitance produced by a parallel plate capacitor is directly proportional to the area of plates and inversely proportional to their separation7. In FiGurE 2, Mathcad is applied to compute and to plot interplane capacitance (per unit area) for two different dielectric materials. These include Isola 370HR (in red) and Rogers 4320 (in blue). The Isola 370HR material is a high performance 180ºC glass transition temperature (Tg) system for PCB applications where maximum thermal performance and reliability are entailed. Rogers 4320 (prepreg) and 4350 (laminate) are glass-reinforced8 ceramic thermosets that are available in several thicknesses with dielectric constant εr = 3.5 and loss tangent Tan(ό) = 0.004. In general, Rogers RO4000 series9 are low-loss materials that can be economically fabricated via standard epoxy/ glass processes. They are designed with excellent high frequency performance and low cost circuit production in mind. The capacitance resulting from two adjacent plane layers plays a crucial role in the power delivery system (PDS) of high-speed boards. Since such parallel plate capacitance is inversely related to the separation of the plane pairs, it is desirable to keep the planes near each other. However, there are two important limitations3 concerning how close the planes can be fabricated. These restrictions relate to the capability of PCB FiGurE 1. A four-layer stack-up. ! OCTOBER 2008 printEd CirCuit dESign & fAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - October 2008

Printed Circuit Design & Fab - October 2008 Contents Our Line Market Watch Around the World Happenings Test and Inspection ROI Tip Jar Interconnect Strategies Final Finish Forum The New Wave in High-Speed Modeling The PCB Design Library Mixed Signal Design Considerations Modeling Conductor Surface Roughness Copper Erosion: The Influence of Metallurgy on Copper Dissolution The Wave of the Future Ad Index Building a Profitable Niche Marketplace Off the Shelf BGA Bulletin

Printed Circuit Design & Fab - October 2008

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