Printed Circuit Design & Fab - October 2008 - (Page 19)

manufacturer to laminate the planes without causing shorts and to preserve minimum dielectric thickness to meet insulation standards. Normally, PCBs cannot provide adequate interplane capacitance5 to successfully meet decoupling requirements below 500 MHz. When this occurs, other decoupling methods, such as employment of discrete capacitors, are then needed. Let us consider the six-layer structure of FiGurE 3, which includes both outer (microstrip) and inner (stripline) traces. For a surface microstrip10 the signal conductor is exposed to air, so the effective dielectric constant will be somewhere between that of air (which equals 1) and the dielectric constant of the substrate below the trace. The signal speed is influenced by the effective dielectric constant with the surface microstrip usually offering the fastest propagation velocity10. After plating, outer-layer traces have greater trace-width variation than innerlayer traces. This implies that stripline traces provide superior impedance control as compared to microstrip lines. However, striplines can cause stubs11 when through-hole vias are used, as illustrated by Figure 3. The configurations depicted by Figures 3a and 3b (which involve connection to stripline traces) result in stubs due to unused via portions (the segments which extend past the vias’ last connecting layer). However, the case of Figure 3c, in which two microstrip transmission lines are connected, can shun via stub formation. Bogatin12 presents an interesting comparison of microstrip vs. stripline traces in terms of impedance control, differential pair coupling, attenuation, far-end crosstalk and routing density. Generally, higher-density PCBs are less expensive, but closely spaced traces can result in crosstalk issues. The PCB manufacturing cost is directly related to the size of the PCB and the number of layers13. pCd&f dr. abE (abbaS) riaZi is a senior staff electronic design scientist with broadcom Corp. in Irvine, CA and can be reached at ariazi@broadcom.com. rEFErEncES 1. Lee W. Ritchey, “Right the First time, a Practical Handbook on High Speed PCb and System Design, Vol. 1” Speeding Edge 2003, Pgs. , 207 – 210. 2. Douglas brooks, “Signal Integrity Issues and Printed Circuit board Design, Prentice Hall PtR, 2003, p. 307. ” 3. Lee W. Ritchey, “Right the First time, a Practical Handbook on High Speed PCb and System Design, Vol. 2, Speeding Edge 2006, ” Pgs. 43-44, Pgs. 66-72. 4. Abe Riazi, “PCb Database Viewing for SI Analyses, Part 1, Printed Circuit Design and ” Manufacture, August 2007, Pgs. 18-19. 5. Henry W. ott, “PCb Stackup Part 1, Henry ” ott Consultants, 2000. 6. Henry W. ott, “PCb Stackup Part 2, Henry ” ott Consultants, 2002. 7. John Ardizzoni, “A Practical Guide to High Speed Printed Circuit board Layout, ” Analog Dialogue 39-09, September (2005). 8. Chad Morgan, “the Impact of PWb Construction on High-Speed Signals, technical ” Seminar, Amp Circuits and Design tyco electronic, 2000. 9. “Ro4000 Series High Frequency Circuit Materials, Data Sheet Ro1.4000, Rogers Cor” poration 2003. 10. “Microstrip transmission line structures, ” Polar Instruments Ltd, Application Note AP122. 11. Abe Riazi, “Via Modeling for High-Speed Simulations, Part 1, Printed Circuit Design and ” Manufacture, September 2003, Pgs. 30-31. 12. Eric bogatin, “Microstrip or Stripline?” Printed Circuit Design and Manufacture, February 2006. 13. “High Density Design With MicroStar bGAs, texas Instruments, Application Report ” ! FiGurE 2. Parallel plane capacitance per unit area versus plane separation for two SPRA471C-April 2003. FiGurE 3. Six-layer PCb stack-up exhibiting via trace connections: (a) through-hole via connecting two stripline traces; (b) connection between a microstrip and a stripline; and (c) via connecting two outer layer traces. Note: only the latter case avoids via stubs. ! different dielectric materials. OCTOBER 2008 printEd CirCuit dESign & fAB 19

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - October 2008

Printed Circuit Design & Fab - October 2008 Contents Our Line Market Watch Around the World Happenings Test and Inspection ROI Tip Jar Interconnect Strategies Final Finish Forum The New Wave in High-Speed Modeling The PCB Design Library Mixed Signal Design Considerations Modeling Conductor Surface Roughness Copper Erosion: The Influence of Metallurgy on Copper Dissolution The Wave of the Future Ad Index Building a Profitable Niche Marketplace Off the Shelf BGA Bulletin

Printed Circuit Design & Fab - October 2008

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