Printed Circuit Design & Fab - October 2008 - (Page 48)

BGA Routing 0.8-mm Pin Pitch bGAs, Part 2 Microvias can reduce the number of signal layers required. tHIS ARtICLE FoCuSES on CHArlES pfEil increasing routing density using microvias. I took a footprint for a Virtex-5 with 1760 pins (1227 I/Os) at 1-mm pitch and converted it to 0.8mm pitch as the basis for the tests. test 2: Stack-up. An HDI stackup was used with 1:2 microvias, 1:3 skip-vias and a through via. The through via was used for fanout of the power and ground pins so they could attach to all the planes and the discrete components on the opposite side of the board. I chose the through via over a buried via because it turns out that the through via is the same size as the buried via would have to be, and the through via is more direct and simple. test 2: Fanout Patterns. It appears that FiGurE 1 presents a different set of fanout patterns than previously described. However, a closer look shows that the same principles of aligning vias and combining different patterns are applied. test 2: Power and Ground. The power (orange) and ground (green) vias are all through vias. Around the perimeter, the ground fanouts have been added a distance away from the ball pads as shown in FiGurE 2. By doing this, an extra route channel is opened between the through vias and the microvias on layer two. test 2: I/o Pins. By using microvias around the perimeter, the effective size of the BGA (to be routed using through vias) has been reduced from 1760 pins to 784 pins. test 2: Layer 1:2 Microvias. The 1:2 microvias are aligned in columns and rows between pairs of ball pads. Because of the 0.8-mm spacing between the ball pads and the rather large space that the through via takes, the microvias are not evenly spaced. In FiGurE 3, the microvias at the top are not aligned in a column. This is because the through vias for the power and ground take up enough space that there isn’t room for the microvias to be aligned. This doesn’t affect the route density. Since there are no additional traces on layer two (purple traces) that have to come through that area, placing the vias horizontally doesn’t block any other traces. This is a general principle when placing the fanout vias. The layer 1:2 microvias are used for the first four rows of pins, and the layer 1:3 microvias are used for the next three rows of pins. Due to the through vias used for the eighth row of pins, the 1:3 microvias had to be packed into a smaller area. This means the 1:3 microvias are not aligned in columns, however, there is a pattern to the madness shown by the pattern in FiGurE 4. test 2: breakout Results. Applying NSEW breakouts with good fanout patterns enables breakouts on large BGAs in five to six signal layers. This method can maintain normal trace widths and clearances. pCd&f charlES PFEil is an engineering director for Mentor Graphics, Systems Design Division. Email: charles_pfeil@ mentor.com. FiGurE 2. Power and ground fanouts. ! ! FiGurE 1. Fanout patterns. 48 ! ! FiGurE 3. Layer 1:2 microvias. FiGurE 4. Layer 3 microvias and excape routes. OCTOBER 2008 printEd CirCuit dESign & fAB http://www.charles_pfeil@mentor.com http://www.charles_pfeil@mentor.com

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - October 2008

Printed Circuit Design & Fab - October 2008 Contents Our Line Market Watch Around the World Happenings Test and Inspection ROI Tip Jar Interconnect Strategies Final Finish Forum The New Wave in High-Speed Modeling The PCB Design Library Mixed Signal Design Considerations Modeling Conductor Surface Roughness Copper Erosion: The Influence of Metallurgy on Copper Dissolution The Wave of the Future Ad Index Building a Profitable Niche Marketplace Off the Shelf BGA Bulletin

Printed Circuit Design & Fab - October 2008

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