Printed Circuit Design & Fab - November 2008 - (Page 24)

SySTEM ModElinG 3D chip-Package-Board MoDeLIng Advanced computing languages will help to develop flexible solver architectures and efficient simulation methods. by VIkRAM JANDHyALA, DIpANJAN GOpE, SwAGATO CHAkRABORTy, FENG LING, XIREN wANG, DEVAN wILLIAMS and JAMES pINGENOT The rapidly growing needs of microelectronics integration have resulted in a mind-boggling variety of innovative packaging concepts. Some of these package types can be seen in FiGurE 1. These technologies create an increasing technical challenge for related layout and design tools, and more critically, the associated electromagnetic and electrical modeling challenges are rising exponentially and creating design bottlenecks and potential design gaps. These challenges are exacerbated by the growing need for integration across chippackage-board-system hierarchies in terms of design, modeling and verification. The concept of an SoC includes multiple chip functionality, as well as digital, analog and mixed-signal functions in a single chip-level system with all associated integration and packaging. In FiGurE 1a, an SoC component comprised of two bond-wire connected dies on one package and a BGAconnected die on another package, stacked in a PoP configuration are shown. Such geometries and connectivities lead to complex electromagnetic situations required to obtain broadband electrical models. In FiGurE 1B, a different approach to stacked die, often used in memory applications, is depicted. In this case, the bond-wires are situated on the top and bottom layers, and a cut is created through the package/printed circuit board to route the bond wires. This can create electromagnetic issues. In FiGurE 1c, multiple dies and stacked dies are connected to a single package layer, potentially creating chip-to-chip crosstalk if not accounted for appropriately. Finally, in FiGurE 1d, 3 DICs are stacked together and routed using TSVs, a recently-developed innovation for WLCSPs and 3 DICs applications. While Figure 1 depicts system-level integration, electromagnetic issues are found at every level of hierarchy. For example, the inclusion of chip effects, necessitated by recent 24 requirements by designers of integrated chip-package-board co-design, drastically changes the requirements on electromagnetic solvers. Several scenarios arise for on-chip electromagnetic modeling. These vary from standard resistancecapacitance extraction for on-chip nets to the inclusion of inductance to modeling of full-wave electromagnetic effects for analog on-chip integrated passives. The presence of digital and analog components and sub-systems necessitates modeling the effect of mixed-signal coupling from high-speed digital sections to sensitive analog subsystems. In addition, the connection of chip-to-package via bond wires, or BGA, creates its own coupling challenge. Redistribution layers (RDL) are required to appropriately connect on-chip signal and power nets to bond wires. Similarly, the locations of onchip I/O pads for BGA connections need to be optimized to !"# $%&'()*+, /01 !$+-#1 2+)0+,(,'1 (3")04(51 6"27"8(1 +,1 6"27"8(1 !696#1 2+,:/8; 1 >/(&1 =/'.1 ?+,>*=/ 1 &/,84(1 >/(1 =/'.1?"4418 1"<<"%1!ABC#1"''"2.)(,'D1 !?# -./0*+,*?+" 1 !-9A#1 2+,:/8; 1 >/(&1 =/'.1 '+01 ",>1 ?+''+)1 &/>(1 ?+,>*=/ ;4(1!E-E#1=/'.1'=+1 &'"27(>1>/(&1=/'.1?+,>*=/ 1 '=+1>/(&1=/'.1ABC1"''"2.)(,'D1 3D Stacked ICs with Through Silicon !># F. /)(,&/+,"41 /,'(8 1 2/ *>/(&1 =/'.1 '.<+;8.*$/4/2+,1 J/"&1 !F$K#1 =/'.1 ABC1 2+,,(2'/+,1 '+1 "1 =":(<*4(J(41 2./0*&2"4(1 0"27"8(1!LM-$6#1 Figure 1: Sample FiGurE 1. Sample ofemerging and existing microelectronicmicroelectronic emerging and existing integration types integration types. printEd CirCuit dESign & fAB NOVEMBER 2008

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - November 2008

Printed Circuit Design & Fab - November 2008 Contents Our Line Market Watch Around the World Happenings ROI Positive Plating Ten Tips to Improve Manufacturability 3D Chip-Package-Board Modeling Improving Circuit Simulation With The Addition Of Real Measurements Ad Index PCB West: Interview with NBS Design Inc. The Influence of Final Finish on Lead-Free Assembly Reliability The Lead-free Soldering Challenges for Peelable Resists Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - November 2008

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