Printed Circuit Design & Fab - November 2008 - (Page 25) SySTEM ModElinG minimize certain metrics such as inductive coupling in power nets. Integrating these geometric intricacies and multi-scale features with all the associated electromagnetic effects from package and board-level interactions is an added challenge for co-design. may also be crosstalk between different metal layers on the same chip or even between two stacked dies, depending on the orientation and the silicon thicknesses. When the signal emerges from the chip, there is possible crosstalk at the I/O pads, RDL layer and between C4 bumps. Crosstalk between bond wires presents itself both for signals from the same chip and from different chips, as in a stacked die case. There are significant crosstalk mechanisms in the package and PCB that must be accounted for. Trace-trace coupling, via-trace coupling, via-via coupling, coupling paths through voids and antipads, current return path spreading (for example with Electromagnetic Modeling Challenges FiGurE 2 depicts instances of the varied electromagnetic (EM) effects that are encountered in chip-package-board co-design. Whether the ultimate goal is power integrity (PI), signal integrity (SI) or electromagnetic interference (EMI) prediction, these EM effects have critical roles to play. The first order effects for signal (and power) propagation are shown by blue arrows. Within the confines of a digital chip, propagation along horizontal (traces) and vertical (via) structures needs to be modeled, including possible reflection at discontinuities and transitions. In an analog, radio frequency (RF) or mixed signal chip, the propagation modeling needs additional detail to model high-frequency effects such as through an onchip inductor or filter. Once the signal leaves the chip, the propagation (and reflection) is effected by discontinuities at the RDL layer or I/O pad where Peelable Resist XZ93-R the signal enters a BGA or bond wire. The signal then encounters another Reduces production costs discontinuity on the other side of the connection, at the package (or PCB in Easy to apply with a smooth finish a CoB) side. Once the signal enters the Withstands multiple wave and package, the dominant propagation through traces and vias is affected by reflow soldering processes reflections caused by impedance disCovers up to 5mm holes continuities including layer changes, antipads and voids and path dimenEasily recognised sion changes. Finally, impedance disdistinct red colour continuities may be encountered at the solder balls. Low odour at HASL Multi-port impedance, admittance or scattering-matrix models that can be used by circuit simulators are directly affected by the dominant first order path effects. In particular, selfworking for you. terms that account for reflection and transmission along a specific net (connected metal) are highly dependent on Sun Chemical these first order effects. The remainder Norton Hill of the models is populated by crosstalk Midsomer Norton Bath BA3 4RT terms that are typically undesirable United Kingdom but are produced by electromagnetic Tel: +44 1761 414 471 coupling. Fax: +44 1761 416 609 In Figure 2, the red arrows depict www.sunchemical.com EM crosstalk mechanisms. Within the chip, cross coupling between traces is an example of crosstalk. There Who makes your life easier and more cost effective? we do. NOVEMBER 2008 printEd CirCuit dESign & fAB 25 http://www.sunchemical.com http://www.sunchemical.com
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - November 2008 Printed Circuit Design & Fab - November 2008 Contents Our Line Market Watch Around the World Happenings ROI Positive Plating Ten Tips to Improve Manufacturability 3D Chip-Package-Board Modeling Improving Circuit Simulation With The Addition Of Real Measurements Ad Index PCB West: Interview with NBS Design Inc. The Influence of Final Finish on Lead-Free Assembly Reliability The Lead-free Soldering Challenges for Peelable Resists Off the Shelf Marketplace BGA Bulletin Printed Circuit Design & Fab - November 2008 Printed Circuit Design & Fab - November 2008 - (Page Intro) Printed Circuit Design & Fab - November 2008 - Printed Circuit Design & Fab - November 2008 (Page Cover1) Printed Circuit Design & Fab - November 2008 - Printed Circuit Design & Fab - November 2008 (Page Cover2) Printed Circuit Design & Fab - November 2008 - Printed Circuit Design & Fab - November 2008 (Page 1) Printed Circuit Design & Fab - November 2008 - Contents (Page 2) Printed Circuit Design & Fab - November 2008 - Contents (Page 3) Printed Circuit Design & Fab - November 2008 - Our Line (Page 4) Printed Circuit Design & Fab - November 2008 - Our Line (Page 5) Printed Circuit Design & Fab - November 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - November 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - November 2008 - Around the World (Page 8) Printed Circuit Design & Fab - November 2008 - Around the World (Page 9) Printed Circuit Design & Fab - November 2008 - Around the World (Page 10) Printed Circuit Design & Fab - November 2008 - Around the World (Page 11) Printed Circuit Design & Fab - November 2008 - Happenings (Page 12) Printed Circuit Design & Fab - November 2008 - Happenings (Page 13) Printed Circuit Design & Fab - November 2008 - ROI (Page 14) Printed Circuit Design & Fab - November 2008 - ROI (Page 15) Printed Circuit Design & Fab - November 2008 - Positive Plating (Page 16) Printed Circuit Design & Fab - November 2008 - Positive Plating (Page 17) Printed Circuit Design & Fab - November 2008 - Ten Tips to Improve Manufacturability (Page 18) Printed Circuit Design & Fab - November 2008 - Ten Tips to Improve Manufacturability (Page 19) Printed Circuit Design & Fab - November 2008 - Ten Tips to Improve Manufacturability (Page 20) Printed Circuit Design & Fab - November 2008 - Ten Tips to Improve Manufacturability (Page 21) Printed Circuit Design & Fab - November 2008 - Ten Tips to Improve Manufacturability (Page 22) Printed Circuit Design & Fab - November 2008 - Ten Tips to Improve Manufacturability (Page 23) Printed Circuit Design & Fab - November 2008 - 3D Chip-Package-Board Modeling (Page 24) Printed Circuit Design & Fab - November 2008 - 3D Chip-Package-Board Modeling (Page 25) Printed Circuit Design & Fab - November 2008 - 3D Chip-Package-Board Modeling (Page 26) Printed Circuit Design & Fab - November 2008 - 3D Chip-Package-Board Modeling (Page 27) Printed Circuit Design & Fab - November 2008 - 3D Chip-Package-Board Modeling (Page 28) Printed Circuit Design & Fab - November 2008 - 3D Chip-Package-Board Modeling (Page 29) Printed Circuit Design & Fab - November 2008 - Improving Circuit Simulation With The Addition Of Real Measurements (Page 30) Printed Circuit Design & Fab - November 2008 - Improving Circuit Simulation With The Addition Of Real Measurements (Page 31) Printed Circuit Design & Fab - November 2008 - Ad Index (Page 32) Printed Circuit Design & Fab - November 2008 - Ad Index (Page 33) Printed Circuit Design & Fab - November 2008 - PCB West: Interview with NBS Design Inc. (Page 34) Printed Circuit Design & Fab - November 2008 - PCB West: Interview with NBS Design Inc. (Page 35) Printed Circuit Design & Fab - November 2008 - The Influence of Final Finish on Lead-Free Assembly Reliability (Page 36) Printed Circuit Design & Fab - November 2008 - The Influence of Final Finish on Lead-Free Assembly Reliability (Page 37) Printed Circuit Design & Fab - November 2008 - The Influence of Final Finish on Lead-Free Assembly Reliability (Page 38) Printed Circuit Design & Fab - November 2008 - The Influence of Final Finish on Lead-Free Assembly Reliability (Page InsertA) Printed Circuit Design & Fab - November 2008 - The Influence of Final Finish on Lead-Free Assembly Reliability (Page InsertB) Printed Circuit Design & Fab - November 2008 - The Influence of Final Finish on Lead-Free Assembly Reliability (Page 39) Printed Circuit Design & Fab - November 2008 - The Lead-free Soldering Challenges for Peelable Resists (Page 40) Printed Circuit Design & Fab - November 2008 - The Lead-free Soldering Challenges for Peelable Resists (Page 41) Printed Circuit Design & Fab - November 2008 - The Lead-free Soldering Challenges for Peelable Resists (Page 42) Printed Circuit Design & Fab - November 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - November 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - November 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - November 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - November 2008 - Marketplace (Page 47) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page Cover4) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S1) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S2) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S3) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S4) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S5) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S6) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S7) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S8) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S9) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S10) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S11) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S12) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S13) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S14) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S15) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S16) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S17) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S18) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S19) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S20) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S21) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S22) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S23) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S24) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S25) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S26) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S27) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S28) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S29) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S30) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S31) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S32) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S33) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S34) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S35) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S36) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S37) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S38) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S39) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S40) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S41) Printed Circuit Design & Fab - November 2008 - BGA Bulletin (Page S42)
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