Printed Circuit Design & Fab - December 2008 - (Page 20)

In order to minimize warping, it is desirable for the stackup to be symmetrical and well balanced25. Normally, an N-layer PCB includes N metal layers separated by N-1 dielectrics, and N should be an even number to avoid warpage19. Another measure to accomplish uniformity is to add dummy copper pads (thieving) to open areas on the PCB’s outer layers. This aids in attaining a uniform copper distribution across the whole board surface. pCd&f dr. aBE (aBBaS) riaZi is a senior staff scientist - hardware development with Broadcom Corporation in Irvine, California and can be reached at ariazi@broadcom.com. FiGurE 7. Hyperlynx Stackup editor. acknowlEdGEMEnt impedance (for single-ended or differential pairs) and then solving for various parameters (trace width, separation). Figure 7 shows a stackup consisting of eight layers. An eight-layer stack5 can satisfy several desirable requirements, including multiple ground and power layers. In this case each signal layer is adjacent to a tightly coupled plane layer, and the signal layers are located between planes layers (and are thereby being well shielded). I am grateful to Messrs. Nanoo (Frederik) Staal, Mohammad Tabatabai, afshin Momtaz, Matthew Isaacs and Neven Pischl of Broadcom Corporation, and Ms. Debi Sorensen of Mentor Graphics Corporation. rEFErEncES 14. Stephen H. Hall, Garrett W. Hall and James a. McCall, “High-Speed Digital System Design, a Handbook of Interconnect Theory and Design Practices, John Wiley and Sons, Inc., 2000, p. 68, pgs. 82-90, ” p. 115. 15. ernie Buterbaugh, “Perfect Timing a design Guide for Clock Generation and Distribution, Cypress Semiconductor Corpora” tion, 2002, Chapter 6. 16. Greg edlund, “Timing analysis and Simulation for Signal Integrity engineers, ” Prentice Hall, 2007, pgs. 196-197. 17. abe riazi, “effects of Plane Splits on HighSpeed Signals, Part 2, Printed Circuit Design ” & Manufacture, april 2007, pgs. 16-17. 18. Istvan Novak and Jason r. Miller, “Frequency-Domain Characterization of Power Distribution Networks, artech House Inc., ” 2007, p. 67. 19. Brian young, “Digital Signal Integrity Modeling and Simulation with Interconnects and Packages, Prentice Hall PTr, 2001, pgs. ” 410 - 413. 20. abe riazi, “effects of Plane Splits on High-Speed Signals, Part 1, Printed Circuit ” Design & Manufacture, February 2007, pgs. 16-17. 21. “Virtex-4 Power System Performance, ” Xilinx Signal Integrity Seminar Series, March 28, 2006. 22. Henry W. Ott, “PCB Stack-Up Part 6, ” Henry Ott Consultants, 2002. 23. eric Bogatin, “Signal Integrity Simplified, Prentice Hall PTr, 2004, p. 260, pgs. ” 489-490. 24. Chuck Troia. “Stackup analysis Using Hyperlynx, Ieee SCV Chapter of the eMC ” Society, January 10, 2006. 25. Patrick Carrier, “Proactive High-Speed PCB Stackup Planning, Mentor Graphics ” Webinar, 2004. 20 printEd CirCuit dESign & fAB DECEMBER 2008 http://www.chemcut.net http://www.chemcut.net

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - December 2008

Printed Circuit Design & Fab - December 2008 Contents Our Line Market Watch Around the World Happenings ROI Global Sourcing EMC for the Real World Interconnect Strategies On the Forefront Final Finish Forum Test and Inspection Electronic System Design Data Management 101 Designers Take on Technology Challenges in 2008 PCB Signal Integrity, Power Integrity and EMC Challenges What’s in a Name? Ad Index PCB Dielectric Materials for High-Speed Applications Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - December 2008

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