Printed Circuit Design & Fab - December 2008 - (Page 34)

SySTEM dESiGn PcB siGNal iNTeGriTy, Power iNTeGriTy and eMc challenges System-level PCB emissions analysis reduces re-spins and EMC issues when PCBs are incorporated into larger systems. by BRAD BRIM For PCB and package designs, the issues of crosstalk, reflections, skew, ringing and other classical signal integrity challenges are pervasive and growing. A meaningful assessment of such effects requires system-level consideration to reliably account for coupling among traces as well as planes, vias and other design structures. System-level analysis also enables consideration of power integrity issues, such as power dissipation, thermal issues, current constraints and power plane noise. Distinctions between signal integrity (SI) and AC power integrity (PI) have blurred, and the need for design-side consideration of EMC has escalated. Simultaneous switching noise (SSN) is a perfect example of the coupling between SI effects and the underlying PI root cause. It is often the case, as for DDR memory circuits; this same SSN situation causes excessive power plane emissions and results in EMC issues. Therefore, system-level SI, PI and EMC are much more closely related than most designers realize. There are many sources of variation in a PDS between the driver and the receiver reference pins. One example would be system-level effects. A DC voltage drop will exist due to the finite conductivity of the copper. Time delay for return currents becomes significant as rise time decreases, and power plane resonances can exist. All of these system-level PI effects are directly reflected in the driver and the receiver transient voltages. Localized effects include return path discontinuities, of which power plane splits and multilayer via transitions are the most common. These discontinuities disrupt flow of the signal (SI effect) and also serve to locally couple energy from the signal into the planes of the global PDS. In fact, they are often a dominant source of power plane noise. In driver and receiver transient voltages, these system-level and localized PI effects are indistinguishable from more classical SI effects. SI and PI are not only related, but also inseparable. FiGurE 1 shows an 8-layer, BGA flip-chip package design for which SI and PI effects are tightly coupled. Ground nets are dark green, power nets are copper and signal nets are other colors. These two differential pair signal nets are modeled at first with circuit analysis. A frequency-dependent W-element model is applied for the differential pairs on the top layer and augmented by a parasitic inductance and capacitance to model the via transitions and ball grid array (BGA) pads. To verify the fidelity of this relatively quick and easy circuit model, a 3D EM analysis is performed. Computational capacity limits imply that the analysis only can be performed on the portion of the package shown in FIGURE 1. The circuit analysis and 3D EM analysis results are nearly identical, and most designers would comfortably consider the design completed. However, performing a system-level analysis of the whole package, including all coupled SI and PI effects, demonstrates a power plane resonance that significantly perturbs the transmitted, reflected and coupled signals on these two differential pairs within the frequency band of interest. FiGurE 2 shows S-parameter results for this design. The 3D DECEMBER 2008 Relationship Between SI and PI Two of the first concepts electrical engineers learn are: current flows in loops and voltage is the potential difference between two points. These two simple concepts mandate the interdependency of SI and PI for printed circuit board (PCB) and package designs. To understand this concept, consider a signal net in a typical PCB design. Current flows in the signal net from driver to receiver, and so-called “return” current flows in the power/ground planes back to the driver to complete the required loop. There is a transient voltage at any point along the signal net. However, this voltage is not uniquely defined in the absence of a second point, often called a “reference” point. The voltage of interest at the driver is between the output pin and a local power/ground pin. Similarly, the voltage of interest at the receiver is between the input pin and a local power/ground pin. As these two voltages reference different local points in the power delivery system (PDS), any variation across the PDS is seen as a variation in these voltages. 34 printEd CirCuit dESign & fAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - December 2008

Printed Circuit Design & Fab - December 2008 Contents Our Line Market Watch Around the World Happenings ROI Global Sourcing EMC for the Real World Interconnect Strategies On the Forefront Final Finish Forum Test and Inspection Electronic System Design Data Management 101 Designers Take on Technology Challenges in 2008 PCB Signal Integrity, Power Integrity and EMC Challenges What’s in a Name? Ad Index PCB Dielectric Materials for High-Speed Applications Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - December 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.