Printed Circuit Design & Fab - December 2008 - (Page 35)

SySTEM dESiGn EM results are shown as solid traces and the system-level results as dashed traces. Two sets of traces with similar but divergent behavior are seen for each type of analysis that results from length differences between the differential pairs. At about 40% of the maximum frequency, the transmitted signal decreases signficantly and the reflection is nearly as large as the transmission. At this frequency, a resonance on the power planes occurs. This global PI issue dramatically affects the perceived SI behavior of the design. Without system-level analysis, this design would have proceeded to manufacturing release and resulted in performance failure for the packaged device. EM analyses are merged into one fully coupled hybrid analysis. All local and global, SI and PI effects are considered by such hybrid analysis. This analysis predicted the plane resonance effect of the complex package design, which circuit analysis precluded and 3D EM analysis did not have the capacity to include in the physical model. However, this type of system-level analysis is more complex than circuit analysis and, therefore, more computational-intensive. Unlike 3D EM analysis, circuit analysis techniques are leveraged only in part, but the advantages include greater capacity and faster analysis of orders-of-magnitude. The package design required only minutes of setup time and seconds to perform circuit analysis, versus 30 minutes of setup time and more than a day of computation time for 3D EM analysis of a portion of the design, not to mention 15 minutes of setup and a few hours of computation time for hybrid analysis of the entire package. SI and PI Analysis Tradeoffs Circuit analysis SI results are very quick and easy to obtain for this design. Transmission line calculators can determine the time delay and the impedance of the differential pairs on the top layers, and via parasitics can be estimated based on previous experience or approximate equations. This circuit model yields enough accuracy for higher-order circuit analyses, such as reflection or timing budgets. Circuit analysis implicitly references all voltages to global node 0, which implies a “global ground” and precludes the consideration of all PI effects. The fidelity of the circuit model could be improved by using 3D EM analysis results for the via transitions. 3D EM analysis of an entire design can yield highly accurate results and is ideal for detailed component design such as crafting a via padstack and return via locations for a high-speed channel. However, significant computational resources are required, and only a small portion of complex PCB or package designs can be considered in a single analysis. In the previous example, the power planes were truncated a reasonable distance from the signal nets of interest – sufficiently far to capture local PI effects of return path discontinuity but not to capture global PI effects (a resonance in this case). Complex designs usually lack the computational capacity for 3D EM analysis to adequately consider PI issues. Not surprisingly, the circuit and 3D EM analysis results were similar. The via transitions and return paths were carefully crafted to avoid localized return path discontinuities. Local to the differential pairs, the circuit analysis assumption of an ideal global ground return path was very close to the structure of the design. The system-level analysis applied is a hybrid combination of circuit analysis and EM analysis. Circuit-level analysis is applied to concatenate the models of all components, such as: traces, vias, pads and wirebonds. 2D and 3D EM computations are applied to obtain electrical models for each circuit component; 3D EM analysis handles power planes. The circuit and the 3D Simultaneous Switching Noise: A Combined SI and PI Challenge SSN challenges are a paragon of inseparable signal effects and power plane behavior. SSN effects exist even if all signal-to-signal coupling is ignored. However, when power plane (return path) effects are ignored, SSN no longer exists. To explore SSN, a simple 4-layer board was defined – a signal layer on top and bottom with one power and one ground plane layer in the middle. As a reference design, a signal net was routed from drivers to receivers on the top layer only. The same signal net was then routed with a significant portion of its length on the bottom layer of the board. This multi-layer routed net was duplicated to form a parallel bus to investigate SSN. These three designs are shown schematically in FiGurE 3. To transition from top layer to bottom layer, the via transitions must pass through both the ground plane and power plane, causing a discontinuity of return path – a PI issue. To enable this return path change from one plane to the other, the planes are connected through decoupling capacitors placed locally to the via transitions. FiGurE 4 shows the transient voltage at the receiver load of these three designs characterized with system-level hybrid analysis. The black trace is the ideal case of routing a single net only on the top layer. The red trace corresponds to routing a single net on both top and bottom layers with multi-layer via transitions. Only slight rise time degradation (skew) is observed in single-layer FiGurE 1. an 8-layer BGa flip-chip package design for which SI and PI effects couple and system-level analysis is required. DECEMBER 2008 FiGurE 2. Frequency response of two high-speed differential pairs. Wide/solid traces are 3D eM SI results. Wide/dashed traces are system-level SI/PI results. printEd CirCuit dESign & fAB 35

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Printed Circuit Design & Fab - December 2008 Contents Our Line Market Watch Around the World Happenings ROI Global Sourcing EMC for the Real World Interconnect Strategies On the Forefront Final Finish Forum Test and Inspection Electronic System Design Data Management 101 Designers Take on Technology Challenges in 2008 PCB Signal Integrity, Power Integrity and EMC Challenges What’s in a Name? Ad Index PCB Dielectric Materials for High-Speed Applications Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - December 2008

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