Printed Circuit Design & Fab - December 2008 - (Page 41)

HS laMinatES taBlE 1. Dielectric materials used in PCB design. performance Low name Dielectric loss Tangent/ Constant (Dk) Dissipation Factor (Df) Cost 4.1 – 4.4 4.0 4.04 3.5 3.75 3.6 3.2 3.48 3.38 0.019 – 0.024 0.022 @ 2.5GHz 0.021 @ 2GHz 0.010 @ 10GHz 0.012 @ 10GHz 0.009 @ 10GHz 0.008 @ 10GHz 0.0037 @ 10GHz 0.0025 @ 10GHz High Medium Low taBlE 2. list of dielectric materials referenced by the various signal traces on the test board. Signal layer L1 (Microstrip) L3 (Stripline) L6 (Stripline) L8 (Microstrip) Dielectric Material that the Trace References Nelco 4000 -13 Nelco 4000 -13 Nelco 4000 - 6 Rogers 4350B Standard FR4 Nelco N4000 - 6 Isola FR 370 HR Medium GETEK Isola FR 408 Nelco 4000 – 13 EP Nelco 4000 – 13 EPSI High Rogers RO4350B Arlon 25N L2, L4, L5 and L7 are solid metal planes stitched together with through hole vias. They act as the return path for all the signal layers. The test board is a single-sided board with all the SMA (subminiature version A) connectors located on the top layer (taBlE 2). The board uses three materials, Nelco 4000-13EP, Nelco 4000-6 and Rogers 4350B, allowing comparisons among different dielectric materials. All the test structures on the board were routed to meet a 50 Ω ± 10% single-ended impedance or a 100 Ω ± 10% for differential impedance. Wide trace widths are used to minimize conductor losses. Two identical differential pairs measuring 25 inches and 40 inches are routed on L1, L3, L6 and L8 to test the performance of various dielectric materials. Differential via design is optimized with ground return vias added next to signal vias to make the vias transparent1. The signal vias on L3 and L6 are back drilled to minimize via stubs. Vector network analyzer (VNA) and eye diagram measurements are used to study the performance of the various dielectric materials in frequency and time domain. FiGurE 2 shows a plot of the differential insertion loss for the 40-inch trace through 8.5 GHz. The measurements are limited to 8.5 GHz due to equipment limitations. Differential insertion loss results indicate the trace on L8 has the best performance because Rogers 4350B has the lowest dissipation factor. The microstrip and stripline traces on L1 and L3 have the next- best performance (Nelco 4000-13), followed by the trace on L6, which references Nelco 4000 - 6 dielectric material. A similar insertion loss behavior, similar to the one illustrated in FIGURE 2, is observed for the 25 inch traces. In addition to the VNA measurements, eye diagram measurements are taken at 10 Gbps using a VOD of 600 mV with a pre-emphasis of 14.5 dB. Near-end and far-end eye diagrams before and after 40 inch traces on L3, L6 and L8 are shown in FiGurE 3. The vertical and the horizontal scale for the eye diagrams are 50 mV/division and 20 ps/division respectively. For cost sensitive designs with lower interconnect lengths, the regular FR-4 type of substrates can still be used with a roughly ~2 dB performance hit compared to expensive substrates. PCB designers can use the built-in, pre-emphasis and equalizer settings in the transceivers available in Stratix GX series of FPGAs to compensate for a portion of the channel loss as the signal traverses through the backplane. For current edge rates of tens of picoseconds (ps), PCB designers can gain an optimal price versus performance solution by moving from regular FR-4-based substrates to a midperformance substrate such as Nelco 4000-13 EPSI, Isola FR-408 or GETEK material. The cost difference is relatively small in comparison to a high-performance type of material. The eye diagram observed on L8 references Rogers material (FIGURE 3) and shows the Vp-p magnitude of 218 mV compared to Vp-p magnitude of 198 mV on L3 and 195 mV on L6. In real applications, the true performance of Rogers material will be better than the observed eye on L8, provided there are no bandwidth limited components like SMA connectors on the board. United States Postal Service Statement of Ownership, Management, and Circulation Publication Title: PRINTED CIRCUIT DESIGN & FAB Publication No.: 1543-6527 Filing Date: 10/1/2008 Issue Frequency: Monthly No. of Issues Published Annually: 12 Annual Subscription Price: $80.00 Complete Mailing Address of Known Office of Publication: UP Media Group Inc. - 2400 Lake Park Drive, Suite 440 - Smyrna, GA 30080; Contact Person: Jennifer Schuler; Telephone: 918-496-1476 8. Complete Mailing Address of Headquarters or General Business Office of Publisher (Not printer): UP Media Group Inc. - 2400 Lake Park Drive, Suite 440 - Smyrna, GA 30080 9. Full Names and Complete Mailing addresses of Publisher, Editor, and Managing Editor: Publisher, Pete Waddell - UP Media Group Inc. - 2400 Lake Park Drive, Suite 440 - Smyrna, GA 30080; Editor, Kathy NargiToth - 2400 Lake Park Drive, Suite 440 - Smyrna, GA 30080; Managing Editor, Katie Haddox - 2400 Lake Park Drive, Suite 440 - Smyrna, GA 30080 10. Owner: UP Media Group, Inc., 2400 Lake Park Drive, Suite 440 - Smyrna, GA 30080 11. Known Bondholders, Mortgagees, and Other Security Holders Owning or Holding 1 Percent or More of Total Amount of Bonds, Mortgages, or Other Securities: None 12. Does not apply 1. 2. 3. 4. 5. 6. 7. 13. Publication Name: PRINTED CIRCUIT DESIGN & FAB 14. Issue Date for Circulation Data Below: October 1, 2008 15. Extent and Nature of Circulation: Average No. copies Each Issue During Preceding 12 Months; No. Copies of Single Issue Published Nearest to Filing date a. Total Number of Copies (Net Press Run): 38,668; 38,758 b. Paid Circulation (By Mail and Outside the Mail): (1) Mailed Outside-County Paid Subscriptions Stated on PS Form 3541 (include paid distribution above nominal rate, advertiser’s proof copies, and exchange copies): 0; 0 (2) Mailed In-County Paid Subscriptions Stated on PS Form 3541 (include paid distribution above nominal rate, advertiser’s proof copies, and exchange copies): 17,363; 22,092 (3) Paid Distribution Outside the Mails Including Sales Through Dealers and Carriers, Street Vendors, Counter Sales and Other Paid Distribution Outside USPS: 20,966; 16,344 (4) Paid Distribution by Other Classes Mailed Through the USPS: 0; 0 c. Total paid and/or Requested Circulation (Sum of 15b (1), (2), (3), and (4)): 38,329; 38,436 d. Free or Nominal Rate Distribution (By Mail and Outside the Mail): (1) Free or Nominal Rate Outside-County Copies Included on PS Form 3541: 0; 0 (2) Free or Nominal Rate In-County Copies Included on PS Form 3541: 0; 0 (3) Free or Nominal Rate Copies Mailed at Other Classes Through the USPS (e.g. First-Class Mail): 0; 0 (4) Free or Nominal Rate Distribution Outside the Mail (Carriers or other means): 220; 222 e. Total Free or Nominal Distribution (Sum of 15d (1), (2), (3), and (4)): 220; 222 f. Total Distribution (Sum of 15c and 15e): 38,549; 38,658 g. Copies not Distributed (See Instructions to Publishers #4 (page #3)): 119; 100 h. Total (Sum of 15f, and g.): 38,668; 38,758 j. Percent Paid and/or Requested Circulation (15c. Divided by 15f times 100): 99.42929778; 99.42573 16. Publication of Statement of Ownership: If the publication is a general publication, this statement is required. Will be printed in the December 2008 issue of this publication. 17. Signature and Title of Editor, Publisher, Business Manager, or Owner: I certify that all information furnished on this form is true and complete. I understand that anyone who furnishes false or misleading information on this form or who omits material or information requested on the form may be subject to criminal sanctions (including fines and imprisonment) and/ or civil sanctions (including multiple damages and civil penalties). (signed) Pete Waddell, October 1, 2008. DECEMBER 2008 printEd CirCuit dESign & fAB 41

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - December 2008

Printed Circuit Design & Fab - December 2008 Contents Our Line Market Watch Around the World Happenings ROI Global Sourcing EMC for the Real World Interconnect Strategies On the Forefront Final Finish Forum Test and Inspection Electronic System Design Data Management 101 Designers Take on Technology Challenges in 2008 PCB Signal Integrity, Power Integrity and EMC Challenges What’s in a Name? Ad Index PCB Dielectric Materials for High-Speed Applications Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - December 2008

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