Printed Circuit Design & Fab - January 2009 - (Page 31)

POwER intEGrity automating the DDRx interface VeRifiCation PRoCeSS Today's standard interfaces are more complex so that both timing and signal integrity need to be a part of the verification process. by DAVE KOHLMEIER If you’re a digital designer, there is a high likelihood that you have used Double Data Rate (DDR/DDR2/DDR3) memories in your designs — they are cheap and fast. Unfortunately, you’ve also probably discovered that verifying the razor-thin timing margins of these interfaces is very complex. With DDR2 pushing 1066 MT/s and DDR3 scheduled for 1600 MT/s, we face the demands of picosecond resolution, including “derating” adjustments to measured delay numbers based on the shape of the receiver waveforms. This is important stuff! This kind of problem begs for a computerized solution. Don’t get me wrong, to an experienced engineer, no single measurement is too complicated; rather, with DDRx, it’s the shear number of possibilities to consider that makes complete manual verification virtually impossible. Fortunately, tools can be built to automate this tedious process and make it possible for any system designer to confidently and efficiently verify DDRx interfaces before committing to PCB prototypes. In a recent survey of tool users, the second most important issue for engineers performing analysis was setup time and complexity. The most important issue is now — and always has been — modeling: finding or creating IBIS models. Even the effort of setting up for DDRx analysis can be eased by using a well-established and proven process of parametergathering user interviews, which ensure that every required step is understandable and completed. Just as important is ensuring that every non-required step is eliminated. PCB-level timing analysis has been going through changes over the last decade. As system designers use larger building blocks connected by standard interfaces to create their products, more of the value for the system comes in the form of integration of these blocks and the software that runs on them. Timing analysis at the PCB level has become focused on verification of these standard interfaces, and the registerJANUARY 2009 level circuit design is now done in RTL and implemented in an FPGA or ASIC, which becomes one of those building blocks. Timing analysis inside an IC remains much as it has in the past, where path-analysis and state-machine-sequence features are extremely important. But for PCB-level analysis, designers now need to validate very specific interfaces (like DDR memory, SATA, PCI Express, etc.) and the paths between the high-level standard blocks. Timing requirements for these standard interfaces are spelled out in great detail, cycle-by-cycle; some are even covered in JEDEC standards. So what a designer needs are tools that are already set up for specific interfaces. The issue users have with setup for analysis is that it can and should be done by the tool vendor, not the user. So the best, most-productive timing tools for PCB-level design are interface-specific verification tools. Let’s take a look first at an example of one of these interfaces, DDR2, and get a feeling for why creating a tool as I have described would be such a productivity boost to the system designer. FiGurE 1. DDR Derating measurements details. PRINTED CIRCUIT DESIGN & FAB 31

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - January 2009

Printed Circuit Design & Fab - January 2009 Contents Our Line Market Watch Around the World Happenings ROI The Signal Doctor Positive Plating Final Finish Forum Making Sense of Laminate Dielectric Properties Design and Fab Tips for Improving Solder Mask Registration Automating the DDRx Interface Verification Process Printed Circuit Design & Fab Annual Buyers Guide: Special Suppliers Section Printed Circuit Design & Fab Annual Buyers Guide: Guide to Products and Services Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - January 2009

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