Printed Circuit Design & Fab - January 2009 - (Page 32)

POwER intEGrity What is DDRx? DDR/DDR2/DDR3 memories have become ubiquitous in digital design exactly because they are cheap (due to the huge volumes) and fast. The speed comes from the fact that data is transferred on both the rising and falling edges of the clocking signal and from the tight margins allowed by "source synchronous" clocking. Source synchronous means that the clock and the data are sourced from the same device. Keeping the clock and the data together eliminates the manufacturing variation you would normally get using a global clock sourced from a different device than the data it’s clocking. Coming from the same device, they share any process (P), voltage (V) and temperature (T) variations. To implement this approach, data is broken up into "lanes,” where each of these lanes, or groups, has its own associated clocking strobe, again sourced from the same device. What’s the big benefit? Speed! But, at the higher data rates, timing isn’t the only problem; now signal integrity enters the picture and on-die termination (ODT) has been added to improve signal quality and to allow for those razor-thin margins. Because we are talking about bi-directionality for some signals, these terminations have to change on-the-fly, to have the proper effect for all types of read and write cycles. That, of course, means they must be taken into account during any kind of simulation. There are many issues, and it really complicates the setup for simulation. calculation (i.e., setup and hold time). Since jitter effects vary based on the stimulus sequence, designers generally use a pseudo-random bit sequence (PRBS) of 256 bits to 1024 bits to try to stimulate something close to the worst-case jitter. It should be noted that it is possible to predict exactly the worst-case pattern and use it — a powerful methodology. Now comes the pièce de résistance: slew-rate derating. Because DDRx margins are so tight, timing specifications have been generated based on “clean” signals with an assumed, nominal slew rate. But of course, this will never occur for all transitions on a real board (remember ISI, signal integrity and terminations, etc.), so a system was established to add or subtract from measured delay times based on the shape of the signal at the receiver. This method of measuring the slew rate (FiGurE 1) must be determined on each edge of each signal at each valid receiver, and the variance from nominal then becomes an index to find the delay-derating value in a lookup table (FiGurE 2). The lookup table is nearly always the JEDEC standard for memory-device receivers, but usually a vendor-specific table for memory controllers. Does that seem complex? Hold on, because there any more things to worry about in trying to simulate one of these interfaces, for example: ■ Each byte lane has its strobe, which must be simulated together with each data bit – with or without crosstalk ■ Read Cycles from each bank, with ODT set properly ■ Write Cycles to each bank, with ODT set properly ■ 4 measurement threshold at receivers ■ Measurements, measurements, measurements That should make the case that setting up for proper validation of a DDRx interface is a huge task, and the actual measurements, in number and complexity, are even worse. So let’s talk about a solution. ISI and Derating With data rates greater than 1 GigaTransactions/second, bit periods are less than one nanosecond, which means there’s a high likelihood on most PCBs that one bit will not have arrived at the receiver before the next bit is sent on its way – an effect called “intersymbol interference” (ISI). In other words, each bit affects subsequent bits due to reflections, crosstalk and other signal integrity problems being still active as the next bit begins its journey. That, in turn, means delay values and slew rates are changing on every edge and are dependent on the specific sequence of values in the bit stream (and the sequence on neighboring nets in the byte lane). Changing delays based on the stimulus to the channel produces jitter, which must be taken into account for each timing PCB Design FiGurE 3 shows a step-by-step wizard. It is constructed by experts in DDRx timing and signal integrity (rather than accountants), and basically interviews you to understand everything about your particular design necessary for successful simulation. Things that affect the verification of your interface — like signal grouping, controller models, stimulus selection, memory speed, physical configurations, on-die termination behavior and derating-table selection– are all saved FiGurE 2. Derating in action. 32 FiGurE 3. DDR Batch Verification Wizard. JANUARY 2009 PRINTED CIRCUIT DESIGN & FAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - January 2009

Printed Circuit Design & Fab - January 2009 Contents Our Line Market Watch Around the World Happenings ROI The Signal Doctor Positive Plating Final Finish Forum Making Sense of Laminate Dielectric Properties Design and Fab Tips for Improving Solder Mask Registration Automating the DDRx Interface Verification Process Printed Circuit Design & Fab Annual Buyers Guide: Special Suppliers Section Printed Circuit Design & Fab Annual Buyers Guide: Guide to Products and Services Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - January 2009

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