Printed Circuit Design & Fab - January 2009 - (Page 33)

POwER intEGrity many other standard interfaces (besides DDRx) — fortunately, there’s no reason that a similarly powerful approach couldn’t be used for those interfaces as well. Conclusion Times have indeed changed. PCB-level timing analysis is very different than it was a decade ago. Today you have more standard interfaces between standard building blocks. Examples are the DDR/DDR2/DDR3 interfaces for memories. These interfaces are, however, much more complex in their behavior than earlier generations, and both timing and signal integrity must be taken into account in verification of the physical implementation. Because of this complexity, measurements, both in number and difficulty, have become manually unmanageable. But it turns out that this is a perfect opportunity to use computer automation to continue to increase the system designer’s productivity. Leave the highlevel thinking to the engineer and the tedium to the tools and the computer! The way forward is obvious. PCD&F FiGurE 4. DDR controller timing model Wizard. in a file to be used as often as needed for this interface, and possibly reused for others like it in the future. (Remember that second issue!) But what about designers’ number one issue - getting models? Fortunately, memory vendors have traditionally been strong at creating IBIS models, both in availability and quality, probably because it made a difference in design wins! DDRx models are no different: designers can go to a memory suppliers’ sites and get IBIS models that include the necessary constructs, such as the ODT options implemented with the IBIS “model selector” keyword. Availability of the IBIS models allows tools to automatically simulate all the termination configurations that occur in the real interface. DDRx controllers are admittedly somewhat different: sure, we can generally get a component-level IBIS model, but we also need a timing model against which to run the interface’s timing checks. These models are not readily available (yet) in a standard form, but their parameters (only a small number) are called out in various datasheets. Still, it’s important to make generating controller models a straightforward task, since our goal is productivity. So, a wizard-based interview can be used to good effect here as well. The wizard walks the user step-by-step through the required parameters (with detailed explanations of what each one means and how it’s usually seen in a data sheet), and at the end, generates the model automatically (with no need to know syntax, etc.). This is exactly what is shown in FiGurE 4: very easy model creation. Imagine that you stepped through the interview process and filled in the answers. Then, with one more button click, the tool goes off and does a complete analysis. For a 32-bit DDR2 interface, that means over 1,500 different simulations and over 100,000 separate measurements! In the end, reports are created, starting at the top with an overall pass/fail indication, and then details on each signal, each setup and hold time and exactly where any violation occurred is detailed. The reports include actual waveform data so the designer can cross-correlate from the report to the actual signals to see precisely what happened. As mentioned early in the article, it’s all about productivity, and that’s exactly the result with a solution like this. I also mentioned in my introduction about JANUARY 2009 davE kohlMEiEr is product line director for Mentor’s PCB Analysis tools, including HyperLynx, ICX and Quiet Expert. He can be contacted at dave_kohlmeier@mentor.com. Specializing in Quickturn Proto's Instant online Quotations & Ordering From Singlesided to 6 layers ML Leadtimes from 48 hrs Full DRC included on all orders Simply send your layout files and order online Internet pioneers with 15 years experience High Quality prototypes at LOW cost's TollFree USA: 1877 3908541 Email: sales@pcb-pool.com www.pcb-pool.com PRINTED CIRCUIT DESIGN & FAB 33 http://www.pcb-pool.com http://www.pcb-pool.com

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - January 2009

Printed Circuit Design & Fab - January 2009 Contents Our Line Market Watch Around the World Happenings ROI The Signal Doctor Positive Plating Final Finish Forum Making Sense of Laminate Dielectric Properties Design and Fab Tips for Improving Solder Mask Registration Automating the DDRx Interface Verification Process Printed Circuit Design & Fab Annual Buyers Guide: Special Suppliers Section Printed Circuit Design & Fab Annual Buyers Guide: Guide to Products and Services Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - January 2009

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