Printed Circuit Design & Fab - February 2009 - (Page 16) BGA Top 10 BGA Breakout Tips A look back at the most important ideas for fanout and routing of BGAs. FOR OVeR A YeAR, I have presented various methods and ideas for fanout and routing of BGAs. This article marks the last of the BGA Bulletin series, and I will be passing the back-page baton to others who will cover additional solutions related to PCB design. I felt it would be appropriate to review the most CHArlES important ideas from previous articles– pfEil hence the Top 10 Tips (in no particular order). The PCD&F issue in which the tip is detailed is included after the title. I hope to write more articles of interest to you in the future; until then, I wish you the best of success with your PCB design challenges! 1. Align Vias (May 2008) Of all the methods, aligning blind vias (mechanically or laser drilled) in columns and rows is the most effective way of increasing the route density. Depending on the size of the via, the route density can increase from 24% to 36% per layer over vias in a standard matrix using the same pitch as the pins. This method is most affective with high-pin-count BGAs and when escaping the device is the primary contributor to the layer count. 2. Push Perimeter Vias (December 2008) When using BGAs that have a pin-pitch less than 0.8 mm, aligning the vias cannot be done because there isn’t enough room between the ball pads for via patterns; in fact most of the time, there is only room to put the vias in the pads. However, if you push the fanout vias for the first two rows of pins around the perimeter and away from the BGA far enough, you can then route the next two rows of pins on the same layer, thereby eliminating one to two layers for the escapes. 3. Adopt HDI (June 2008) The smaller feature sizes available when using HDI enable great improvements in route density and will reduce your layer count significantly. A new book, “HDI Handbook,” is completed and is available at http://www. hdihandbook.com. The authors include: Happy Holden, John Andresakis, Eric Bogatin, Michael Carano, Karen Carpenter, Karl H. Dietz, Mark Laing, Christophe Vaucher, Per Viklund and Mat Wuensch. This book provides incredible depth and detail about HDI. 4. Spread Vias-In-Pad (December 2008) When using via-in-pad methods, you can spread the vias within the pads and potentially open up a channel to route differential pairs without splitting them. 5. Use Ground Fanouts (April 2008) It is tempting to minimize the number of ground fanout vias in order to increase route density; however, there is a 16 trade-off with this method. It can affect power and signal integrity by reducing the ground return paths. Ground ball pads are almost always distributed in some kind of pattern around the BGA, and they are not in nice columns or rows. Therefore, not using fanout vias will not open up route channels. I recommend using a through-via or a combination of blind and buried vias for each ground pin to ensure the ground planes are highly connected, providing excellent return paths. 6. Adjust Patterns Locally (May 2008) When using via patterns to increase route density, the vias for the differential pairs sometimes are spread apart. Each set of fanouts for the differential pairs should be reviewed and moved locally in order to fulfill your coupling and phase matching requirements. 7. Layer-Biased Via Patterns (August 2008) If you have only two to four layers to route a BGA, then escaping in all directions on each layer makes sense because of the extreme route density. If you have more than four layers to route, then applying a layer-biased concept, where the escape routes obey the layer bias, enables more efficient routing– especially if an autorouter is used. 8. Use Regions (July 2008) Applying different via patterns in regions is an effective way to increase route density when you have a variety of via spans to work with. For example, you could use a 1:2 via span on the outer four rows of ball pad fanouts (Region 1), a 1:3 via span for the next four rows in from the perimeter (Region 2) and through-vias for the fanout in the center of the BGA which is usually for power and ground distribution. 9. Investigate Any-Layer Vias (November 2008) Of all the HDI via types, the Any-Layer-Vias hold the greatest promise for effective fanout and routing of finepitch BGAs. These vias may start and end on any layer, thereby giving you the greatest flexibility and route density. I have heard of a 12-layer board using any-layer vias, and over time, I expect this technology to be applied to boards up to 20 layers. 10. Prepare for Further Minituration (January 2009) Although the highest pin-count BGAs (over 1500 pins) are still at 1 mm pin pitch, there are many 0.6-mm pitch BGAs with hundreds of pins. The minituration will continue, and new methods for the packages and fanouts will be required. pCd&f charlES PFEil is an engineering director for Mentor Graphics, Systems Design Division. email: charles_pfeil@mentor. com. FEBRUARY 2009 printEd CirCuit dESign & fAB http://www.hdihandbook.com http://www.hdihandbook.com
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - February 2009 Printed Circuit Design & Fab - February 2009 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar BGA Bulletin Interconnect Strategies Final Finsh Forum Defects Database Embedded Active Components In Multilayer LCP Packages Simulation: The Need for Speed Advanced Registration Systems The DC Design Squeeze Ad Index Do You Really Want a Better Autorouter? Designing With Conductive Materials, Part 1 Off th eShelf Marketplace On the Forefront Printed Circuit Design & Fab - February 2009 Printed Circuit Design & Fab - February 2009 - (Page Intro) Printed Circuit Design & Fab - February 2009 - Printed Circuit Design & Fab - February 2009 (Page Cover1) Printed Circuit Design & Fab - February 2009 - Printed Circuit Design & Fab - February 2009 (Page Cover2) Printed Circuit Design & Fab - February 2009 - Printed Circuit Design & Fab - February 2009 (Page 1) Printed Circuit Design & Fab - February 2009 - Contents (Page 2) Printed Circuit Design & Fab - February 2009 - Contents (Page 3) Printed Circuit Design & Fab - February 2009 - Our Line (Page 4) Printed Circuit Design & Fab - February 2009 - Our Line (Page 5) Printed Circuit Design & Fab - February 2009 - Market Watch (Page 6) Printed Circuit Design & Fab - February 2009 - Market Watch (Page 7) Printed Circuit Design & Fab - February 2009 - Around the World (Page 8) Printed Circuit Design & Fab - February 2009 - Around the World (Page 9) Printed Circuit Design & Fab - February 2009 - Around the World (Page 10) Printed Circuit Design & Fab - February 2009 - Around the World (Page 11) Printed Circuit Design & Fab - February 2009 - Happenings (Page 12) Printed Circuit Design & Fab - February 2009 - Happenings (Page 13) Printed Circuit Design & Fab - February 2009 - ROI (Page 14) Printed Circuit Design & Fab - February 2009 - Tip Jar (Page 15) Printed Circuit Design & Fab - February 2009 - BGA Bulletin (Page 16) Printed Circuit Design & Fab - February 2009 - BGA Bulletin (Page P1) Printed Circuit Design & Fab - February 2009 - BGA Bulletin (Page P2) Printed Circuit Design & Fab - February 2009 - BGA Bulletin (Page P3) Printed Circuit Design & Fab - February 2009 - BGA Bulletin (Page P4) Printed Circuit Design & Fab - February 2009 - BGA Bulletin (Page 17) Printed Circuit Design & Fab - February 2009 - Interconnect Strategies (Page 18) Printed Circuit Design & Fab - February 2009 - Interconnect Strategies (Page 19) Printed Circuit Design & Fab - February 2009 - Final Finsh Forum (Page 20) Printed Circuit Design & Fab - February 2009 - Defects Database (Page 21) Printed Circuit Design & Fab - February 2009 - Embedded Active Components In Multilayer LCP Packages (Page 22) Printed Circuit Design & Fab - February 2009 - Embedded Active Components In Multilayer LCP Packages (Page 23) Printed Circuit Design & Fab - February 2009 - Embedded Active Components In Multilayer LCP Packages (Page 24) Printed Circuit Design & Fab - February 2009 - Embedded Active Components In Multilayer LCP Packages (Page 25) Printed Circuit Design & Fab - February 2009 - Simulation: The Need for Speed (Page 26) Printed Circuit Design & Fab - February 2009 - Simulation: The Need for Speed (Page 27) Printed Circuit Design & Fab - February 2009 - Simulation: The Need for Speed (Page 28) Printed Circuit Design & Fab - February 2009 - Simulation: The Need for Speed (Page 29) Printed Circuit Design & Fab - February 2009 - Advanced Registration Systems (Page 30) Printed Circuit Design & Fab - February 2009 - Advanced Registration Systems (Page 31) Printed Circuit Design & Fab - February 2009 - Advanced Registration Systems (Page 32) Printed Circuit Design & Fab - February 2009 - Advanced Registration Systems (Page 33) Printed Circuit Design & Fab - February 2009 - The DC Design Squeeze (Page 34) Printed Circuit Design & Fab - February 2009 - The DC Design Squeeze (Page 35) Printed Circuit Design & Fab - February 2009 - The DC Design Squeeze (Page 36) Printed Circuit Design & Fab - February 2009 - Ad Index (Page 37) Printed Circuit Design & Fab - February 2009 - Do You Really Want a Better Autorouter? (Page 38) Printed Circuit Design & Fab - February 2009 - Do You Really Want a Better Autorouter? (Page 39) Printed Circuit Design & Fab - February 2009 - Designing With Conductive Materials, Part 1 (Page 40) Printed Circuit Design & Fab - February 2009 - Designing With Conductive Materials, Part 1 (Page 41) Printed Circuit Design & Fab - February 2009 - Designing With Conductive Materials, Part 1 (Page 42) Printed Circuit Design & Fab - February 2009 - Off th eShelf (Page 43) Printed Circuit Design & Fab - February 2009 - Marketplace (Page 44) Printed Circuit Design & Fab - February 2009 - Marketplace (Page 45) Printed Circuit Design & Fab - February 2009 - Marketplace (Page 46) Printed Circuit Design & Fab - February 2009 - Marketplace (Page 47) Printed Circuit Design & Fab - February 2009 - On the Forefront (Page 48) Printed Circuit Design & Fab - February 2009 - On the Forefront (Page Cover3) Printed Circuit Design & Fab - February 2009 - On the Forefront (Page Cover4)
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