Printed Circuit Design & Fab - February 2009 - (Page 28)

HS SiMulation FiGurE 6. Interconnect Selection Model Matrix. FiGurE 5. IO Buffer Selection Model Matrix. picoseconds. The only way to be able to validate a tight timing budget like this is through simulation. The fact that there are so many variables in a memory bus, such as memory controller edge rate, termination scheme at the DIMMs and PCB trace impedance, makes the need for simulation even greater. While following manufacturers’ design guidelines can help, PCB designers are finding that in order to design a robust system that can account for full system level affects, like SSN (Simultaneous Switching Noise), performing simulations is the only way to get the correct data. Selecting The Right IO Buffer Simulation Model Where PCB designers were once dealing with PCI 133 MHz interfaces, they are now dealing with PCI Express Generation 2.0 interfaces with speeds up to 5 Gbps, shown in FiGurE 3. As the interface speeds have increased, so has the complexity of the simulation model representing the input/output buffer of the device. Now PCB designers have to contend with on-die termination, differential signaling and adaptive equalization in order to get designs to work. Traditionally, SPICE has been used to model the input/output buffers of a device using transistor level process data. However, by using process data, a company faces the risk of revealing the intellectual property of its design to the competition. Since there are also many different flavors of SPICE, supported by different EDA vendors, a SPICE model of an IO buffer is only good for the particular version of SPICE that can leave customers tied to a specific design tool. The IBIS specification was developed to address these concerns. An IBIS model replaces a SPICE model for use in PCB simulations in order to evaluate signal quality and timing. An IBIS model represents an IO buffer (FiGurE 4) as a behavioral model, rather than as process data. The model consists of current-voltage (I-V) data curves representing the transistors in certain modes of operation. Another side benefit of using an IBIS model is that it typically simulates much faster than a transistor-based SPICE model because it is behavioral. The IBIS specification also allows for advanced modeling, such as including external Verilog-AMS and VHDL-AMS models and an added algorithmic modeling format called IBIS-AMI for SerDes design. For advanced circuit design techniques like pre-emphasis, it requires using advanced simulation-modeling techniques that I call ‘macromodeling’. I define a macromodel as a hybrid simulation model that represents an IO buffer using a mix of modeling formats such as SPICE, IBIS and other model28 ing languages. For example, macromodeling would be using a traditional IBIS model with an external VHDL-AMS model to represent a SerDes IO buffer with pre-emphasis. It can be confusing to determine which model format type is best for a particular simulation. To aid in this selection, one can setup a model matrix, as shown in FiGurE 5, to set the criteria for selecting IO buffer models. By using this type of selection matrix, a PCB designer can identify the best model format to use in a simulation. I typically recommend starting off with a traditional IBIS model if available. IBIS models enjoy wide support from both silicon and EDA vendors, so obtaining and being able to simulate an IBIS model is readily available. An IBIS model will also have faster simulation run times than a SPICE model. While reducing a simulation run time from three minutes to 30 seconds may not seem like a lot for one individual simulation, it can add up if you are doing hundreds or thousands of simulations. This is often the case for a memory bus configured with multiple DIMM modules that needs to have the timing verified across process and for multiple memory vendors. However, a traditional IBIS model has some limitations on modeling advanced circuit design techniques like pre-emphasis and equalization. At this point, it is a trade-off for the PCB designer to use either the traditional SPICE- based model or create a macromodel. The advantages of using the SPICE model are that design features are already there, and the model should work without any additional setup. Being tied to a specific SPICE engine and increased simulation run times are disadvantages. By selecting a macromodel, the PCB designer has the most flexibility to model the IO buffer with advanced features while limiting the simulation run time. There are some special cases, like high-speed SerDes above 5 Gbps, where a model format such as IBIS-AMI is perfectly acceptable. Interconnect Simulation Models Need To Be Accurate PCB designers need to be able to model and simulate different interconnect types such as packages, vias, PCB traces, connectors and cables. While an IO buffer model enjoys different modeling standards, an interconnect model can take many shapes and sizes. The more popular formats that will be discussed here are: Lossless Lumped RLC, Lossy RLGC Matrix and S-parameters. A lossless lumped RLC model is an equivalent-lumped approximation suited for an electrically short interconnect. Sometimes, these types of models are called Single-Line Models (SLMs) and Multi-Line Models (MLMs). A Multi-Line Model includes the additional coupling between elements in the interconnect. A FEBRUARY 2009 printEd CirCuit dESign & fAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - February 2009

Printed Circuit Design & Fab - February 2009 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar BGA Bulletin Interconnect Strategies Final Finsh Forum Defects Database Embedded Active Components In Multilayer LCP Packages Simulation: The Need for Speed Advanced Registration Systems The DC Design Squeeze Ad Index Do You Really Want a Better Autorouter? Designing With Conductive Materials, Part 1 Off th eShelf Marketplace On the Forefront

Printed Circuit Design & Fab - February 2009

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