Printed Circuit Design & Fab - February 2009 - (Page 35)

SiMulation FiGurE 2. A design team that is very effective in controlling IR drop benefits from additional head room in managing AC noise. Basic DC Analysis Early DC assessments help determine power distribution basics such as the best available entry point for power, layer stackup choices and estimates for the amount of copper needed to carry the current. A design team may anticipate a processor will draw 80 amps to 100 amps, and the design will require six routing layers. Traditionally, voltage drop analysis for a design like this utilized spreadsheet estimations that considered resistivity for simplified geometry profiles. For simple designs with uniform plane shapes and a single voltage to consider, this can be sufficient if the margin is ample. Things get much more complicated, however, for designs with multiple sinks, various voltage levels and irregular plane shapes. Further, spreadsheets cannot perform important via current calculations, and beyond this, it is a rare design team that finds itself with margin to spare. Designs with 10 or more unique power domains almost always require splitting power planes, and, many times, there is a need for copper area fills on signal layers, which adds to the complexity. In cases like this, spreadsheet-based calculations fall short and generate a false sense of security. FiGurE 3. Selection of the best VRM remote sense location helps manage DC voltage drop and provides an 18% margin improvement. DC Simulation Numerical DC analysis has emerged as a critical step in the design of high-performance packages and PCBs. Simulations determine if power nets are properly connected and confirm exactly how good the connections are. DC analysis tools go beyond spreadsheet calculations with accuracy that reduces the risk of field failure. Implemented early in the design cycle, these tools support planning and move with the product as layout proceeds. Before detailed layout, DC analysis is useful for allocating budgets between the package and board. It can help determine the appropriate plane shapes and splits, where to position the multiple VRMs (voltage regulator module) and can identify preferred remote sense line locations. DC power distribution can strongly influence layer stackup. DC simulations enable design teams to produce the most robust system possible without wasting plane layers. Performing what-if assessments with various source and sink locations before routing begins enables design refinement while there is maximum flexibility. The most advanced tools available today include adaptive triangular meshing to precisely model actual design geometries, including irregular shapes on every layer. This is critical to accurately simulate designs with via fields and planes that include arbitrary cuts, and simulation with a finite element engine tuned to DC analysis assures the most accurate results FEBRUARY 2009 possible. Since most electronic products today are required to run close to targeted limits, accuracy is at a premium. Designs benefiting from very accurate DC analysis can yield downstream savings from reduced layer counts and the avoidance of expensive active cooling strategies where passive approaches suffice. For large designs or multi-board simulations, analysis speed is an important issue. When simulations are tuned specifically to DC studies, run times are faster. A simulation tool optimized for DC calculations generally runs 3x to 10x faster than a general purpose AC / DC simulator. This enables the kind of rapid what-if assessment and design tuning needed for the best designs. Quick DRC style pass / fail checks enable users to readily identify problems. Interactive what-if visualization is helpful in providing users with cues about insufficient power or excess current density. With this information, users can make adjustments to the design and confirm a robust implementation. Fast turn around enables physical layout tasks to continue unimpeded avoiding wasteful backtracking and rework. VRM Tuning Power supplies are linked to chips by a power delivery system that includes a VRM, printed circuit board and IC package. Where possible, VRMs are located on the same board as the loads, and generally, the VRM dominates performance up to about 100 KHz. Higher performance chips often include local VRMs. With effective DC analysis that considers nominal voltage levels and minimum input tolerances, sinks that are out-of-spec are quickly identified, and issues can be addressed by increasing VRM compensation. VRM position, rotation and adjustment play a significant role in keeping designs within tolerances. Still, it can be tricky to understand how much the VRM nominal output voltage can be safely raised to maximize compensation. DC simulators are effectively used to assess design alternatives. At times, users will want to define the ratio between the VRMs in a group to control current split. Similarly, some users may want to control their most complex power nets individually at selected chip locations. With more capable tools, sink printEd CirCuit dESign & fAB 35

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - February 2009

Printed Circuit Design & Fab - February 2009 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar BGA Bulletin Interconnect Strategies Final Finsh Forum Defects Database Embedded Active Components In Multilayer LCP Packages Simulation: The Need for Speed Advanced Registration Systems The DC Design Squeeze Ad Index Do You Really Want a Better Autorouter? Designing With Conductive Materials, Part 1 Off th eShelf Marketplace On the Forefront

Printed Circuit Design & Fab - February 2009

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