Printed Circuit Design & Fab - February 2009 - (Page 36)

SiMulation FiGurE 4. Via and plane density issues associated with typical plane shape irregularities. location information can be further refined on a per-pin basis with values that are added through text files. Generally, this data comes from chip-level simulations. This per-pin information further refines the accuracy of multi-domain (chip / package / board) current estimates. FiGurE 5. Safely removing 2 layers from a space constrained board design. Remote Sense Line Location Adding a remote VRM sense location plays a vital role in helping designers efficiently meet end-to-end voltage margins by detecting changes in loading and controlling voltage levels. If there is an increase in current, the VRM raises voltage output to compensate and to manage the additional IR drop.If the current is decreased, the voltage level similarly can be adjusted. The location of the VRM remote sense line is critical for effective performance. Unfortunately, it is not always easy to identify the best location for a VRM remote sense, particularly when multiple devices are involved. Having the sense located in the best possible position is critical, this single design optimization can increase the ability to meet targeted thresholds and significantly improve overall voltage margin efficiency by 10% to 20% compared to seemingly reasonable alternative locations. Even expert level power engineers find it difficult to pinpoint the best location using judgment and experience alone. DC analysis tools can be extremely helpful in understanding the effectiveness of simulated remote sense location scenarios. As observed in FiGurE 3, recent breakthroughs also automate pinpointing the optimized location and avoid the need to iteratively simulate the myriad of possible implementations. Results for nearly every design show this one-step optimization approach significantly shaves DC margin. Current Density Challenges Accurately understanding plane current density can be a critical project success factor. Chip current requirements are so high that plane and via current density constraints must be carefully managed to avoid current distribution hot spots that introduce unnecessary thermal stress. Contributing to the challenge are higher component, via and routing densities combined with a desire to minimize layer counts and copper costs. Current flow to components produces heat that must be transferred to surrounding structures efficiently, or component 36 junction temperatures will rise, reducing product reliability. This possibility leads to a requirement that device junction and overall board temperatures are controlled to ensure they remain below specified limits. It also necessitates a comprehensive understanding of current density and the heat generated by the design’s current flow. Often, this is easier said than done. In a design with thousands of vias, how do you find the one that will lead to field failure or identify which bumps and wirebonds are susceptible? The need to control current flow into vias is critical because high current density leads to temperature rise. It is very difficult to determine which via will fail, and beyond that, the failure of one via can trigger a cascade of via failures. Swiss cheese via fields and unusual plane shapes (FiGurE 4) increase current density challenges, without careful analysis, this can lead to end-product reliability problems. Vias can act like fuses creating an overall system failure, and most designs include a few vias that exceed anticipated current limits. When failures occur, the cause is not immediately obvious even to expert eyes. While a designer may assume a neighboring plane will dissipate heat, planes with via fields will not have the anticipated effect. The risk is also high in areas where plane shapes neck-down or in areas with dynamic plane cuts. Excessive plane current density leads to thermal stress, dielectric failure and even fires in PCB organic substrates. As design layout progresses, analysis can effectively identify risks. Areas in the design that neck-down contribute to excessive IR drop, and in cases where the neck-down area does not lead to an IR drop problem, thermal stress can be created. Sometimes this happens because of unusual cuts in plane structures for mounting holes and the like. It is also typical that in the final stages of design, there is a need to route a signal net on a plane layer; these plane cuts impact current flow and lead to areas of excessive density. It is nearly impossible to avoid making some adjustment in plane layers as layout progresses, but by simulating them, issues can be quickly identified and mitigated without impeding design progress. Comprehensive current density assessments can identify opportunities to safely reduce the plane layer count, leading to substantial cost savings. In one case, illustrated in FiGurE 5, a telecom equipment supplier hit the physical limit for board FEBRUARY 2009 printEd CirCuit dESign & fAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - February 2009

Printed Circuit Design & Fab - February 2009 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar BGA Bulletin Interconnect Strategies Final Finsh Forum Defects Database Embedded Active Components In Multilayer LCP Packages Simulation: The Need for Speed Advanced Registration Systems The DC Design Squeeze Ad Index Do You Really Want a Better Autorouter? Designing With Conductive Materials, Part 1 Off th eShelf Marketplace On the Forefront

Printed Circuit Design & Fab - February 2009

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