Printed Circuit Design & Fab - November 2007 - (Page 16)

PACKAGING A New Approach for FINER PITCH PACKAGE-ON-PACKAGE in Mobile Devices µPILR technology can reduce the standoff between the PCB and the bottom package and increase mechanical board-level reliability, improving drop-test performance. by MANISHA SHARMA The past decade has seen a tremendous market demand for driving more and more functionality into applications in the mobile space. The cell phone is a prime example of this trend as our daily communication, computing and consumer electronics needs merge from discreet, handheld units into one multifunctional device. The basic cell phone took off in the 1990s as a novelty with voice only. The introduction of the color screen in 2000 and the camera module in 2002 were innovative developments that dramatically changed the way we view our mobile devices. Several other applications have been integrated, and today, our cell phones offer advanced functions such as digital TV, GPS, MP3 technology and more security as we search the web, enabling our on-the-go lifestyles. The integration and miniaturization of all components within the device has become a necessity to achieve the reduced form factor and weight demanded by consumers. The silicon stacking industry has seen many revolutions, with memory stacking for a memory subsystem to system-inpackage (SiP) with the inclusion of logic devices. Die stacking logic and memory was a quick way of initially achieving the desired form factor, but the cost was not sustainable long term due to the compound yield loss of the total package. In 2005, the introduction of package-on-package (PoP) into the industry allowed the logic and memory sub-system packages to be tested separately and reduce the cost. FIGURE 1 shows an illustration of the production PoP in mobile phones today. PoP technologies have become a main standard for these applications, allowing designers to match technological advancements in functionality with increasingly smaller form factors. This article will discuss two main approaches for miniaturizing PoP via finer pitch: memory sub-system package stacked on package with one logic die or two logic die. Market Trends for Package-on-Package The current industry standard for the PoP inter-package ball-out interface is at 0.65-mm ball pitch, and package sizes range from 11 mm x 11 mm to 16 mm x 16 mm with varying architectures. The bottom package (for the processor) is 0.5mm pitch with a custom ball-out based on the processors. Tessera recently conducted a study to evaluate pitch trends for the logic IC in mobile applications from 2003 to 2007. The study examined 110 mobile phone teardowns from Portelligent (portelligent.com). In 2003, approximately 30% of these ICs were at 0.5-mm pitch, and the rest ranged up to 0.8-mm pitch. Today, over 98% of these logic ICs are now at 0.5-mm pitch. The increasing number of applications in mobile devices and subsequent higher performance demands require higher pin counts, which typically increases size. This requires the footprint to remain the same or become smaller. Accommodating these higher pin counts in such a footprint will require smaller pitch. There are several ways the industry is reducing or maintaining the overall footprint. This article will discuss NOVEMBER 2007 FIGURE 1. Illustration of the production PoP in mobile phones today. 16 PRINTED CIRCUIT DESIGN & FAB http://portelligent.com

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Printed Circuit Design & Fab - November 2007

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