Printed Circuit Design & Fab - November 2007 - (Page 17)

FIGURE 2b. SEM image (higher magnification) of a µPILR contact (125 µm height with 80 µm tip). FIGURE 2a. SEM image of a µPILR contact (125 µm height with 80 µm tip). two main approaches when dealing with PoP stacking. The first option is to reduce the solder ball pitch, which reduces the packages X-Y size. Logic IC packages are trending toward 0.4-mm pitch, driving the top memory sub-system package to reduce from the current 0.65 mm to 0.5-mm pitch. This option will achieve a smaller package size of the one component as its performance increases from one generation to the next. The second option allows for higher integration while maintaining or reducing the solder ball pitch and, in return, reducing the overall footprint of two or more packages into one. Stacking a second logic IC into the bottom package will increase the package size for the PoP but will reduce the overall combined size of the two separate packages (one stand-alone logic package and one PoP). This option will also increase the I/O count, and the package can remain at 0.5-mm pitch to maintain good routing or reduce to 0.4-mm pitch for size benefits. In either case, the top memory subsystem package can remain at 0.65-mm pitch to maintain the memory interface I/O count for the larger package. die thinning and/or reduce the bump height. There is also a cost premium associated with lower wire-bond loop heights, and reduced mechanical reliability for lower bump heights for flip chips. All these solutions increase performance risk and cost due to die thinning and handling. The second option – stacking two logic die in the bottom package – will require an increased clearance between the two packages. Increasing solder ball size to achieve this increased clearance will require higher pitch for the memory sub-system to avoid solder bridging. In addition, the higher pitch will reduce the I/O count for the package-to-package interface if the same X-Y size is to be maintained. These challenges are difficult to overcome within the current technology window while maintaining the cost and risk targets. The industry is examining innovative new approaches to take packaging technology to the next level. One new option is the Micro Pin Interconnect Layer (µPILR) technology developed by Tessera, which addresses many of these challenges. µPILR Technology for PoP The µPILR technology platform utilizes conical-shaped, solid copper contacts plated with nickel/copper. This can be used in multiple types of interconnections: 1. IC-to-package substrate interconnections 2. Package-to-PCB and/or PoP interconnections 3. Interlayer via connections within package substrates, flexible printed circuits or high-density PCBs. FIGURES 2a and 2b show SEM images of this contact. This article will mainly discuss the package-to-package and PCB-to-package interconnections for PoP. PoP Challenges with New Market Trends These two PoP approaches will enable increased integration and reduced overall form factor to allow for continued increases in performance and applications in mobile devices. However, both options have their challenges. For the first option, the reduced pitch on the top package will result in smaller clearance between the two packages. A logic die can be connected to its substrate via wire bond or flip chip. Currently, the clearance between two packages using either interconnection method for 0.65-mm pitch is approximately 0.270 mm to 0.320 mm. When the top package pitch is reduced to 0.5 mm, the clearance will reduce to approximately 0.220 mm due to the smaller solder ball used for this smaller pitch. In turn, this will require reduced height in the logic IC. Reducing the height for wire-bonded die would mean die thinning to ≤75 µm and/or reducing the wire bond loop height. Reducing flip-chip height will also require NOVEMBER 2007 FIGURE 3. Drop test data using µPILR showing first failures for 0.4 mm, 0.5 mm and 0.65 mm pitch. PRINTED CIRCUIT DESIGN & FAB 17

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Printed Circuit Design & Fab - November 2007

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