Printed Circuit Design & Fab - November 2007 - (Page 18)

PACKAGING would need to remain at approximately 0.270 mm. Figure 5 (left side) shows that a solder ball-only solution cannot meet this requirement unless the solder ball size is increased, which increases the risk of solder bridging. Using µPILR, Figure 5 (middle), allows better control of the standoff to achieve the desired clearance by forming a column-like structure. Since µPILR can provide improved joint reliability, the same calculation was done with a smaller pad opening, as shown in Figure 5 on the right side. This allows for a higher margin for the standoff. The standoff for the contact using µPILR can be further increased by increasing the total solder volume. Surface-mount experiments showed that increased solder content enables a higher standoff at the same finer pitch without bridging, mainly because µPILR causes the joint to form a column-like structure, which is more robust than a solderonly joint. FIGURE 6 shows a SEM picture of a 0.125-mm µPILR copper pin surrounded by solder to form an interconnect with a standoff of 0.540 mm. A clearance this high also facilitates the second approach of stacking two logic ICs in the bottom package of a PoP as mentioned earlier. As the industry continues the trend toward tighter integration in mobile devices, stacking two logic devices in the bottom package for PoP will allow for higher performance and smaller overall form factor. However, this results in a thicker mold cap height on the bottom package, which requires a larger standoff clearance between the two packages. At even larger pitches such as 0.65 mm, solder ball interconnect cannot overcome this mold cap height. However, by applying the concept of increased standoff ability with the µPILR technology to this application at 0.65-mm pitch, designers will be able to realize more integration between the logic and memory. Testing will be conducted for daisy-chain, board-level reliability on the µPILR PoP test vehicle with one die as shown in Figure 4 at 0.5 mm, and with two die at 0.65-mm pitch in the bottom package and up to three die in the top packages. The data will be available in late 2007 and early 2008, respectively. The test vehicle will be RoHS compliant with a halogen-free material set. Testing will cover JEDEC JESD22B111 for drop (1500 gn, 0.5 ms pulse, 30 drops), JEDEC JESD22-A104 Condition G for temperature cycling (-40˚C to +125˚C until 63% fail, 10 minute dwell, 10˚C/minute ramp rate; continuous monitoring of resistance) and JEDEC-9702 for monotonic bend test (4-Point Bend; 5000 µStrain/s). Package assembly with µPILR technology uses standard semiconductor assembly equipment for all major processes, including die placement, wire bonding and overmold. The surface-mount technology required for µPILR is dependent on the resulting standoff needs, since the copper pins are coated with nickel and immersion gold to allow for high-strength adhesion of solder. If the interconnect standoff is to be minimized for height reduction between the bottom package and PCB, for example, then the ball attach process at package assembly can be eliminated, and the surface mount can be performed by optimizing the solder paste content on the PCB. The µPILR package can then be picked, placed and reflowed in the same manner as any other component. For higher standoff requirements, such as between packages, solder can be pre-applied to the µPILR copper pins. Additional solder paste or solder balls can be placed NOVEMBER 2007 FIGURE 4. Test Vehicle for µPILR PoP with one logic and three memory die at <1.2 mm total package height. The introduction of the solid copper contact within a solder joint provides better ability to control and hold standoff while maintaining solder interconnect reliability at the board and package-to-package level of the PoP. This technology can reduce the standoff between the PCB and the bottom package by more than 50% to allow overall package height reduction. Due to the increased surface area between the copper and solder when using µPILR, there is an increase in mechanical board-level reliability, especially drop test. FIGURE 3 illustrates initial drop test data where the addition of the copper pin shows late first failures using JESD22B111 drop test conditions. The test vehicle for the data was on a 10 mm x 10 mm package size with the full area populated with µPILR contacts. The drop test was performed on this test vehicle with multiple pitches – 0.65 mm, 0.5 mm and 0.4 mm – using 196, 324 and 529 total µPILR contacts, respectively. To simulate an actual device, the silicon size used was 6.5 mm x 6.5 mm x 150 µm. This was attached to the top surface of the substrate using paste die attached material. The overmold height for the package was 450 µm over the substrate. A theoretical stack-up analysis of the test vehicle (shown in FIGURE 4) using the tolerance stacking methodology shows that less than 1.2 mm total height can be achieved. The test vehicle consists of one die in a bottom package at 0.4-mm pitch, three die in the top package at 0.5-mm pitch µPILR and a two-layer µPILR substrate (top and bottom). The ability of µPILR to control standoff at the packageto-package interconnect level allows for higher clearance between the two packages while maintaining the needed finer pitch. FIGURE 5 (left and middle side) shows the difference between the resulting standoffs for solder ball and µPILR PoP, respectively, at the package-to-package interface using the same solder ball diameter and pad opening. Figure 5 (right side) also shows the resulting standoff with a smaller solder ball and pad opening. This data was calculated using an in-house developed software utility. This software calculates the resulting shape of the solder (diameter and height) based on the initial volume of solder. The final shape can be calculated for different cases including solder reflowed on a pad, solder ball reflowed to make the joint between two packages, or between package and PCB. The calculations are based on the assumption that the surface tension dominates, and hence, the free solder surface is spherical. If the package weight per interconnect ratio is high enough, then gravity will have a significant effect, which is not accounted for in this tool. For standard packages, package weight/interconnect ratio is small enough that the results from this tool are quite accurate when compared to actual observed data. To meet market demands for a smaller 0.5-mm pitch at the package-to-package interface and to keep the risk factor on the logic device as low as possible, the desired stand-off 18 PRINTED CIRCUIT DESIGN & FAB

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