Printed Circuit Design & Fab - November 2007 - (Page 23)

is with drilled sequential lamination. FIGURE 3a shows the 12-layer multilayer stackup composed of two 4-layer multilayers, drilled and plated and then laminated to two rigid cores with three pieces of prepreg. Board size has been reduced 23% to 50 sq. in. and drill sized reduced to a 0.008˝ finished hole size (FHS) for the four-layer composite multilayers but remains at 0.010˝ FHS for the through-holes. prepreg that also has vias. This unique scheme allows any layer to connect to any other layer. Board size has been reduced 50.8% to 32 sq. in. and the microvia drill size to a 0.006˝ FHS. This stackup does not have any through holes! PCB Basis A 16-layer through-hole board was selected as the printed circuit basis for the different design strategies. The 1517 pin FPBGA with 50 Ω single-ended drivers and 100 Ω differential data pairs dominates the board. Two other BGAs of 940 pins and 498 pins also complicate the design. These are connected to 16 flash memories with 144 pins at 0.8 mm. The multilayer board is 10.0˝ x 7.8˝ with a full 1.5V power plane and a 2.5V, 1.25V, 5V split power plane. A top view can be seen in FIGURE 4. TV2: Staggered Sequential Microvia Build-up The staggered via IPC Type III stackup is the most popular and versatile. FIGURE 3b shows the 10-layer multilayer stackup comprised of one-buildup layer on each side of an eight-layer multilayer board, mechanical/laser drilled and plated and then laminated to a piece of prepreg and foil. Board size has been reduced 30.8% to 45 sq. in. and microvia drill size to a 0.006˝ FHS for the two buildup layers. The composite multilayer hole size remains at a 0.010˝ FHS for the through holes and buried vias. TV3: Stacked Sequential Microvia Build-up The stacked via IPC Type III stackup is now becoming popular in North America. FIGURE 3c shows the eightlayer multilayer stackup composed of two-buildup layers on each side of a four-layer multilayer, mechanical/laser drilled and plated and then laminated twice to pieces of prepreg and foil. Board size has been reduced 43.1% to 37 sq. in. and the microvia drill size to 0.006˝ FHS for the two buildup layers. The composite multilayer remains at 0.010˝ FHS for the through holes and buried vias. TV4: Co-Laminated Any Layer Microvia Build-up The any-layer via is an IPC Type VI stackup. This type is popular in Japan and Asia for its high density. Nearly nine of the HDI Vintages in Figure 2 are this type. FIGURE 3d shows the eight-layer multilayer stackup composed of four double-sided layer pair cores. Each is mechanically or laser drilled and plated, etched, and then tested. These are then laminated with NOVEMBER 2007 PRINTED CIRCUIT DESIGN & FAB 23 http://www.processphotonics.com http://www.processphotonics.com

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Printed Circuit Design & Fab - November 2007

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