Printed Circuit Design & Fab - November 2007 - (Page 24)

HDI DESIGN AND FAB placement eliminated many of the larger drilled throughholes and drilled buried vias. A circuit copy & place command was used to replicate the breakout pattern keeping in mind the layer bias so that the autorouter would pick up the trace hangars. The autorouter was optimized for each type of blind/ buried via structure and layer-pairing. Autorouting was performed first by critical nets and build-up layers, then tuned and smoothed. After the maximum utilization of the blind vias, the larger through-hole and buried vias were allowed. The fact that the autorouter could push and shove traces and microvias made for the most flexibility in their being placed but in not disturbing the critical nets. TABLE 1. Summary of the five alternative stackups and via structures. Setting Up HDI Routing Using an EDA tool with HDI design capability, setting up any of the various 21 different HDI architectures was very simple. The Constraint Editor System (CES) allowed impedance, crosstalk, wiring, spacing and timing to be easily specified for all the high-speed single-end and differential nets, as well as by “Net Class” and “I/O” constraints. FIGURE 5 shows three of the “configuration” menus that set up the different blind and buried via structures. Menu a is the blind/buried/through-hole via span as well as via diameter and electrical characteristics. Menu b holds the via-to-via clearances for stacked, inset or staggered vias. Menu c is the dynamic planes generator for controlling planes spacing, copper pouring and electrical characteristics. The three complex BGAs were all fanned-out semi-automatically using the unique blind/buried via available for that structure. The combination of layer-stackup and microvia Performance of Microvias The results of the four sets of design runs were quite remarkable. Via geometry, clearances and stackup have a profound affect on breakout and routing. This was the overriding variable that permitted a smaller board with fewer layers. With fewer through-holes, innerlayer routing density was two to three times greater because of the additional space freed up with the removal of the large drilled holes. The alternative stackups of the HDI boards also allowed microvias to replace as many as 45% of the through holes. The routing layer-pairs of X-Y using microvias as layer-transition greatly reduced the need for buried vias and through holes. The results can be seen in TABLE 1. Summary of Through-Hole versus HDI Structures To summarize the positive effect blind and buried microvias have on board size, layers and density, the chart in FIGURE 6 has N Layers A THRU-HOLE N blind via* buried via B HDI BLIND 1+N+1 L1-L2 none C HDI BL/BU 1+bN+1 L1-L2 L2-L(N-1) D 1BU BLIND 1+N+1 skip via L1-L3 L2-L(N-1) E 2BU BLIND 2+N+2 staggered L1-L2, L2-L3 none F 2BU BL.BU 2+bN+2 skip via L1-L3 L2-L(N-1) G 2BU BL.BU 2+bN+2 staggered L1-L2, L2-L3 L3-L(N-2) RCI DEN RCI DEN RCI DEN RCI DEN RCI DEN RCI DEN RCI DEN 4L 6L 8L 10L 12L 14L 16L 18L 20L 22L 24L 26L 28L 30L 32L 34L 36L 38L 40L 0.62 0.78 1.00 1.30 1.70 2.24 2.97 3.92 5.14 6.67 8.53 10.68 13.09 15.63 18.17 20.59 22.79 24.68 26.26 20 20 30 40 60 70 80 100 105 110 125 130 135 140 145 150 160 180 200 0.83 0.99 1.21 1.51 1.92 2.48 3.22 4.21 5.48 7.08 9.03 11.30 13.83 16.50 19.17 21.69 23.96 25.91 40 60 120 200 210 220 260 300 360 400 460 500 540 580 620 660 700 740 1.05 1.24 1.49 1.83 2.31 2.95 3.81 4.95 6.41 8.23 10.41 12.92 15.65 18.47 21.21 23.73 25.94 80 160 180 210 230 250 300 400 500 600 700 1.26 1.46 1.74 2.11 2.62 3.32 4.25 5.47 7.04 8.99 11.32 13.96 16.82 19.73 22.53 25.09 135 200 240 260 300 360 420 480 1.38 1.60 1.90 2.30 2.85 3.61 4.61 5.93 7.62 9.70 12.17 14.96 17.93 20.94 23.79 135 200 240 260 300 360 420 480 -1.74 2.06 2.50 3.10 3.91 5.00 6.42 8.23 10.45 13.07 16.00 19.09 22.18 -260 300 400 600 800 1000 1250 -1.91 2.25 2.73 3.37 4.25 5.43 6.96 8.90 11.27 14.04 17.11 20.32 23.48 -280 320 440 650 860 1100 1350 FIGURE 6. Density and relative cost index for through hole to various HDI structures. 24 PRINTED CIRCUIT DESIGN & FAB NOVEMBER 2007

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Printed Circuit Design & Fab - November 2007

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