Printed Circuit Design & Fab - November 2007 - (Page 36) METRIC DESIGN Metric Pitch BGA and Micro BGA ROUTING SOLUTIONS For designers, working with metric units increases performance and overall quality. by TOM HAUSHERR The following paper provides via fan out and trace routing solutions for various metric pitch BGA (Ball Grid Array) packages. To solve the metric pitch BGA dilemma, one should have a basic understanding of the metric feature sizes for the following: ■ BGA ball sizes and BGA land pattern pad construction ■ BGA via anatomy ■ Trace/space ■ Trace and via routing grid ■ Differential pairs ■ HDI hole size/annular ring. To begin, BGA pad size is determined by the ball size as seen in TABLE 1 from IPC-7351A. It is very important to note that IPC prefers the maximum material condition for all BGA land sizes; they do not use the nominal land diameter, but do use the maximum land variation diameter. IPC-7351A has a 3-Tier BGA formula for placement courtyards that use BGA ball size to calculate an adequate TABLE 1. Land approximation (mm) for collapsible placement courtyard for BGA rework tools. If the BGA has a large ball size, larger rework equipment is necessary to unsolder the large solder volume. With a small ball size, the placement courtyard can be smaller as less heat is then required to unsolder the BGA component for rework. However, the end user may not plan to rework the BGA if it fails. In that case, there is no need to have a robust placement courtyard. The BGA, like any component, needs assembly workmanship space and requires the minimum 0.5 mm placement courtyard boundary for pick and place machines and for the tools to manually assemble it. TABLE 2, also from IPC 7351A, represents the 3-Tier scenario and the different placement courtyard sizes. The anatomy of the metric via is based on the 0.05 mm universal grid for PCB design layout. The features of the metric via should always be sized in 0.05 mm increments for the following: ■ Pad size ■ Hole size ■ Solder mask size TABLE 2. BGA density levels. LEAD PART MINIMUM (LEAST) DENSITY LEVEL C 15% reduction below nominal ball diameter 5% increase above nominal ball or column diameter MEDIAN (NOMINAL) DENSITY LEVEL B 20% reduction below nominal ball diameter MAXIMUM (MOST) DENSITY LEVEL A 25% reduction below nominal ball diameter solder balls. NOMINAL REDUCTION LAND BALL PATTERN DIAMETER DENSITY LEVEL 0.75 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.17 0.15 25% 25% 25% 25% 20% 20% 20% 20% 20% 20% 15% 15% 15% A A A A B B B B B B C C C NOMINAL LAND DIAMETER 0.55 0.50 0.45 0.40 0.40 0.35 0.30 0.30 0.25 0.20 0.17 0.15 0.13 LAND VARIATION 0.60 - 0.50 0.55 - 0.45 0.50 - 0.40 0.45 - 0.35 0.45 - 0.35 0.40 - 0.30 0.35 - 0.25 0.35 - 0.25 0.25 - 0.20 0.20 - 0.17 0.20 - 0.14 0.18 - 0.12 0.15 - 0.10 Courtyard excess Round-off factor Periphery noncollapsing ball or column Periphery collapsing ball 10% increase 15% increase above above nominal ball or nominal ball or column diameter column diameter Round off to the nearest two place decimal, i.e., 1.00, 1.05, 1.10, 1.15 0.50 1.00 2.00 Note: Ball Grid Array (BGA) construction and land pattern development are described in 14.1 and 14.4. Column Grid Array (CGA) construction and land pattern development are described in 14.1.3 and 14.4. 36 PRINTED CIRCUIT DESIGN & FAB NOVEMBER 2007
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - November 2007 Printed Circuit Design & Fab - November 2007 Contents Our Line Market Watch Around the World Happenings ROI Packaging HDI Design and Fab Plating Design Tools Metric Design Productronica Product Preview Marketplace Ad Index The Signal Doctor Printed Circuit Design & Fab - November 2007 Printed Circuit Design & Fab - November 2007 - Printed Circuit Design & Fab - November 2007 (Page Cover1) Printed Circuit Design & Fab - November 2007 - Printed Circuit Design & Fab - November 2007 (Page Cover2) Printed Circuit Design & Fab - November 2007 - Printed Circuit Design & Fab - November 2007 (Page 1) Printed Circuit Design & Fab - November 2007 - Contents (Page 2) Printed Circuit Design & Fab - November 2007 - Contents (Page 3) Printed Circuit Design & Fab - November 2007 - Our Line (Page 4) Printed Circuit Design & Fab - November 2007 - Our Line (Page 5) Printed Circuit Design & Fab - November 2007 - Market Watch (Page 6) Printed Circuit Design & Fab - November 2007 - Market Watch (Page 7) Printed Circuit Design & Fab - November 2007 - Around the World (Page 8) Printed Circuit Design & Fab - November 2007 - Around the World (Page 9) Printed Circuit Design & Fab - November 2007 - Around the World (Page 10) Printed Circuit Design & Fab - November 2007 - Around the World (Page 11) Printed Circuit Design & Fab - November 2007 - Happenings (Page 12) Printed Circuit Design & Fab - November 2007 - Happenings (Page 13) Printed Circuit Design & Fab - November 2007 - ROI (Page 14) Printed Circuit Design & Fab - November 2007 - ROI (Page 15) Printed Circuit Design & Fab - November 2007 - Packaging (Page 16) Printed Circuit Design & Fab - November 2007 - Packaging (Page 16A) Printed Circuit Design & Fab - November 2007 - Packaging (Page 16B) Printed Circuit Design & Fab - November 2007 - Packaging (Page 17) Printed Circuit Design & Fab - November 2007 - Packaging (Page 18) Printed Circuit Design & Fab - November 2007 - Packaging (Page 19) Printed Circuit Design & Fab - November 2007 - HDI Design and Fab (Page 20) Printed Circuit Design & Fab - November 2007 - HDI Design and Fab (Page 21) Printed Circuit Design & Fab - November 2007 - HDI Design and Fab (Page 22) Printed Circuit Design & Fab - November 2007 - HDI Design and Fab (Page 23) Printed Circuit Design & Fab - November 2007 - HDI Design and Fab (Page 24) Printed Circuit Design & Fab - November 2007 - HDI Design and Fab (Page 24A) Printed Circuit Design & Fab - November 2007 - HDI Design and Fab (Page 24B) Printed Circuit Design & Fab - November 2007 - HDI Design and Fab (Page 24C) Printed Circuit Design & Fab - November 2007 - HDI Design and Fab (Page 24D) Printed Circuit Design & Fab - November 2007 - HDI Design and Fab (Page 25) Printed Circuit Design & Fab - November 2007 - HDI Design and Fab (Page 26) Printed Circuit Design & Fab - November 2007 - Plating (Page 27) Printed Circuit Design & Fab - November 2007 - Plating (Page 28) Printed Circuit Design & Fab - November 2007 - Plating (Page 29) Printed Circuit Design & Fab - November 2007 - Plating (Page 30) Printed Circuit Design & Fab - November 2007 - Plating (Page 31) Printed Circuit Design & Fab - November 2007 - Design Tools (Page 32) Printed Circuit Design & Fab - November 2007 - Design Tools (Page 33) Printed Circuit Design & Fab - November 2007 - Design Tools (Page 34) Printed Circuit Design & Fab - November 2007 - Design Tools (Page 35) Printed Circuit Design & Fab - November 2007 - Metric Design (Page 36) Printed Circuit Design & Fab - November 2007 - Metric Design (Page 37) Printed Circuit Design & Fab - November 2007 - Metric Design (Page 38) Printed Circuit Design & Fab - November 2007 - Metric Design (Page 39) Printed Circuit Design & Fab - November 2007 - Metric Design (Page 40) Printed Circuit Design & Fab - November 2007 - Metric Design (Page 41) Printed Circuit Design & Fab - November 2007 - Productronica Product Preview (Page 42) Printed Circuit Design & Fab - November 2007 - Productronica Product Preview (Page 43) Printed Circuit Design & Fab - November 2007 - Marketplace (Page 44) Printed Circuit Design & Fab - November 2007 - Marketplace (Page 45) Printed Circuit Design & Fab - November 2007 - Marketplace (Page 46) Printed Circuit Design & Fab - November 2007 - Ad Index (Page 47) Printed Circuit Design & Fab - November 2007 - The Signal Doctor (Page 48) Printed Circuit Design & Fab - November 2007 - The Signal Doctor (Page Cover3) Printed Circuit Design & Fab - November 2007 - The Signal Doctor (Page Cover4)
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