Printed Circuit Design & Fab - December 2007 - (Page 31)

RF DESIGN power/ground planes. Again, we have an area ruled by “black magic;” “This is what we’ve always done so it must be good …” Still, there are some published papers that can help us better understand what really happens to the power and ground planes. If we inject a current between two parallel plates, they will radiate due to something called parallel plate excitation that allows signals to propagate between the plates. Trust me, if the “parallel plates” are your ground plane, you will want to suppress this. Typically, we have multiple ground layers, and we pepper the ground areas and stitch the edges of ground areas with vias to short the planes together preventing this propagation mode in the ground plane.3 Interestingly, via array acts as band pass filters at high frequencies. The via to via spacing controls the pass band poles, and we will soon see that the viato-via spacing is very important4. Takeshi Yuasa et al. have found the pass band frequency to be as shown in FIGURE 3 where r is the relative permittivity of the dielectric material, and c is the speed of light, a function of via diameter, via spacing and dielectric material3. However, this calculated frequency is not the same as the usable upper limit! The space enclosed by four via holes forms a cavity, which will resonate at about 0.65X the center frequency (Fc)3. This becomes the real upper limit. At resonance, the grounding effect of the via array is lost, and the structure will no longer prevent the parallel plate mode excitation. From this, it is clear that how we arrange the vias, their diameter and their pitch is important, and does impact the effectiveness of the via fencing and via peppering. always found. The tool integrations of the traditional flow make it very cumbersome to set up and run this type of simulation with incremental updates while the circuit design and layout are in progress. Typically, Gerber, DXF or GDS-II files are used, which means that all design intent is lost in the interface due to primitive data formats. New methodologies combined with new design tools that use a more elegant integration, where design data keeps its “intelligence,” make it possible to keep the intent of the design and run repeated simulations very quickly. This makes it possible to quickly identify problems caused by circuit interaction and correct them as you go along in a “correct by design” flow. Interactions will happen. Identifying and correcting these interactions as the system design evolves, rather than in the end, offers the potential to yield much shorter design cycles and fewer of those cycles. This is because the earlier the issues can be identified, the easier they can be corrected. Making substantial changes to a dense and complete design can take a very long time. PCD&F PER VIKLUND is director of IC packaging & RF with Mentor Graphics, Systems Design Division; per_viklund@ mentor.com. REFERENCES 1. Wu, Xin, Mahammad H. Ke~mani and Omar M. Ramahi. ”Mitigating Multilayer PCB Power Bus Radiation Through Novel Mesh Fencing Techniques, Mechanical Engineer” ing Department, Electrical and Computer Engineering Department, and CALCE Electronic Products and Systems Center, University of Maryland College Park, MD. 2. Ponchak, George E., Donghoon Chen, JongGwan Yook, and Linda P B. Katehi. ”Char. acterization of Plated Via Hole Fences for Isolation Between Stripline Circuits in LTCC Packages, IEEE THIF61. ” 3. Yuasa, Takeshi, Tamotsu Nishino, and Hideyuki Oh-hashi. ”Simple Design Formula for Parallel Plate Mode Suppression by Ground ViaHoles, Mitsubishi Electric Corp., 5-1-1 Ofuna, ” Kamakura, Kanagawa, 247-8501 Japan. 4. Tischler, Thorsten, Matthias Rudolph, Andreas Kilk, and Wolfgang Heinrich. ”Via Arrays for Grounding in Multilayer Packaging Frequency Limits and Design Rules, Ferdinand-Braun-Institut für Höchstfrequenztechnik (FBH), D-12489 Berlin, Germany. Verification In a classic RF design flow, RF modules are simulated in the RF design environment (initially), not taking into account the actual PCB implementation. Verification includes repeating that simulation, but now with all known PCB features included, such as surrounding non-RF signals, metal planes and shapes, via stitching, via peppering and other techniques. Ideally, the differences in simulation results are negligible, but the reality is that serious issues are DECEMBER 2007 PRINTED CIRCUIT DESIGN & FAB Quick Circuit Prototyping Systems Design • Build • Test • Shorten the process any Shape • any Size • any Material Brass • Cu • PTFE • Ceramic QuickCircuit Systems Your shortcut to success! This is Design. www.T-Tech.com 31 http://www.T-Tech.com http://www.T-Tech.com

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Printed Circuit Design & Fab - December 2007 Contents Our Line Market Watch Around the World Happenings ROI 2007 PCB Designer Salary Survey Interconnect Strategies Positive Plating RF Design Ad Index Noise Reduction Supply Chain DfM Off the Shelf Marketplace The Signal Doctor

Printed Circuit Design & Fab - December 2007

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