Printed Circuit Design & Fab - February 2008 - (Page 17)

Timing Analysis Techniques for Digital PCB Successful design/characterization of PCB high-speed interfaces frequently demand analyses of timing margins and jitter. THE DIGITAL SIGNAL integrity as a discipline1 came into existence in the 1960s, and three main signaling schemes have since emerged. These signaling methods include common clock, source synchronous and high-speed serial. Many SI issues in modern digital interfaces are caused by reflection, crossDR. ABE talk, attenuation, resonances, and power RIAZI distribution noise. However, the actual failure mechanism does not involve voltage waveforms (at input of the receiver ICs), but a timing relationship1 between those waveforms and the clock that samples the signal. It has been observed that “ninety percent of signal integrity problems are timing problems 2.” Several concepts and mathematical formulae governing common clock and source synchronous timing were described in previous columns3,4. One way to apply timing equations is by generating a spreadsheet to compute allowable worst (and best) case flight times5 and timing budgets. FIGURE 1 displays section of a timing spreadsheet created utilizing Microsoft Excel. The spreadsheet was generated to summarize the timing results for various nets of a high-speed parallel bus. The column entries display net names, driver reference designations (plus pin names), receiver designations (and pin names), minimum and maximum rise times, minimum and maximum flight times, setup and hold margins. For a bi-directional bus, it is necessary to solve the min/max flight times for each signal direction. Such spreadsheets can readily indicate which nets have failed setup or hold timing margins and hence require an improvement to meet timing requirements. Timing budgets may be also presented in table format6. Several programs are available to aid system timing analysis and verification. Such software include Timing Designer from Forte Design Systems, Timing Diagrammer Pro from Synaptic CAD, Inc, TimingTool (a free, intranet-based timingtool.com timing diagram editor) and Tau7. Eye diagrams also offer an effective means for ascertaining the setup / hold margins for source synchronous buses8, centering clock transitions in the middle of the data eye2 and for deriving timing equations4. FIGURE 2 illustrates how setup and hold margins for a source synchronous signals may be determined via an eye diagram. Here T1 represents timing margin, T2 equals skew, T3 is setup time and T4 is hold time, T5 is “valid before time” (i.e., the time before the strobe occurs when the data signal will be valid). T6 is “valid after time” (i.e., the time after the strobe occurs for which the data is still valid). When timing failures (or signal quality violations) are detected for a signal net, the signal performance may improved by altering/enhancing termination, topology9, 10 or technology (sometimes called the “the three Ts”). As clock frequencies increase, timing becomes more critical11. Timing margins for parallel bus architectures diminish and signal flight times (propagation delays) are reduced to picoseconds. Because such tight tolerances are often not feasible to obtain, the serial data bus architectures have emerged and gained popularity for the fastest systems. Eye diagrams provide a preferred/intuitive means for timing analysis of high-speed differential serial links (with embedded clocks). Eye height is the eye opening in the amplitude domain and eye width relates to signal timing and jitter12. Eye masks are applied to more easily determine pass/fail conditions. Eye width and height are bounded by a mask, and any violation of the mask boundaries can indicate non-compliance12. An example of eye diagram together with eye mask (shown in blue) is provided by FIGURE 3. It displays signal captured (at the receiver end) for a 1.5 Gb/s Serial ATA (SATA) bus. FIGURE 3 depicts a sufficiently open eye. When the eye is closed, there are various techniques such as pre-emphasis or equalization13 which may be applied to open the eye. Pseudo-random binary sequence (PRBS) patterns14 are frequently used as stimulus (to the channel) to generate eye contours. PRBS is a data pattern that attempts to replicate truly random data yet it is completely deterministic. PRBS patterns have length of [(2^N)-1], such as [(2^7) – 1] = 127 bits. Each signaling standard (e.g. SATA, PCI Express, XAUI, HDMI, etc.) specifies how to capture data for eye measurements (including clock recovery method) and the FIGURE 1. A timing spreadsheet using Microsoft Excel. FEBRUARY 2008 FIGURE 2. Utilizing eye diagram for determining setup and hold margins. PRINTED CIRCUIT DESIGN & FAB 17 http://timingtool.com http://timingtool.com

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Printed Circuit Design & Fab - February 2008

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