Printed Circuit Design & Fab - February 2008 - (Page 19)

INTERCONNECT STRATEGIES FIGURE 3. Eye diagram together with eye mask belonging to a high-speed serial link. FIGURE 4. Total jitter measured using an Agilent Infiniium Real-Time DSO. masks that ascertain compliance or non-compliance12. Many high-speed serial links incorporate 8b/10b encoding12 to guarantee minimum transition of data (to aid receiver recover clock) and apply scrambler to reduce EMI. Certain test equipment such as Agilent Infiniium DSO81204A (12 GHz 40 GSa/s) allow jitter measurements on ultra-fast serial signals and can display total jitter, random jitter, deterministic jitter, data-dependent jitter, as well as pattern and periodic jitter. An example is illustrated by FIGURE 4, which decomposes jitter into subcomponents to facilitate debugging. Figure 4 also displays histogram and bit error rate (BER) bathtub curves. Such displays are useful for quickly correlating15 multiple answers, detecting Intersysmbol interference (ISI), and knowing whether the device meets the standard. ISI can be caused by transmission line losses (which degrade signal rise time) and lead to degradation of the eye diagram13. BER is an important metric16 for quantifying the performance of high-speed serial architectures. The BER and jitter analyses/testing have become a necessity to assure performance requirements for highspeed serial links, particularly due to the increasing data speeds. PCD&F DR. ABE (ABBAS) RIAZI is a senior staff electronic scientist with ServerWorks (a Broadcom Company) in Santa Clara, CA. REFERENCES 1. Greg Edlund, ”Timing Analysis and Simulation for Signal Integrity Engineers” Prentice , Hall, 2007, P PP 13-14. .2, . 2. Jim Peterson, “Timing Numbers from ICX - What Do We Do With Them?” Mentor Graphics International User Conference May 2-5, 2006. 3. Abe Riazi, “ Timing Analysis Principles for Digital PCBs, Part 2” Printed Circuit Design , & Manufacture, June 2006, PP 20-21. . 4. Abe Riazi, “ Timing Analysis Principles for Digital PCBs, Part 3” Printed Circuit Design , & Manufacture, August 2006, PP 16-17. . 5. Tod Westerhoff, “Closing the loop between timing analysis and signal integrity“ , Cadence Online Seminar, August 28, 2000. 6. “DDR2 Design Guide For Two-DIMM Systems” Micron Technical Note, TN-47-01. 7. Tom Granberg, “Handbook of Digital Tech, niques for High-Speed Design“ Prentice Hall, 2004“ PP 583-586. . 8. Stephen H. Hall, Garrett W. Hall, James A. McCall, “High-Speed Digital Design, A Handbook of Interconnect Theory and Design Practices, “John Wiley and Sons Inc., 2000, PP 186-190. . 9. Bill Hargin, “Managing Signal Quality” Xcell , Journal, Second Quarter, 2005. 10. Abe Riazi, “Signal Quality Assessment” , Printed Circuit Design & Manufacture, June 2007. PP 16-17 . 11. Roy G. Leventhal and Lynne Green, “Semiconductor Modeling For Simulating Signal, Power, and Electromagnetic Integrity” , Springer, 2006, P 30. . 12. “The Basics of Serial Data Compliance and Validation Measurements”Tektronix. , 13. Eric Bogatin, Signal Integrity – Simplified, Prentice Hall, 2004, PP 333-335, PP . . 398-399. 14. Min Wang, Henri Maramis, Donald Telian, Kevin Chung “New Techniques for Designing and Analyzing Multi-GigaHertz Serial Links” DesignConn 2005. , 15. “Agilent 86100C Infiniium DCA-J, the fast, est way to the right answer” Agilent Technologies. 16. Mike P Li, and Dennis Petrich, “Charac. terization and Production Testing At 3.2-5.0 GB/s for PCI Express II and FB DIMM” 2006 , Wavecrest Corp. CHICAGO. SPRING. YOU. MAY 2008. Join us for PCB East 2008 May 11-16 in Tinley Park, IL. www.pcbeast.com ACKNOWLEDGEMENTS Special thanks to Richard Kuo for reviewing the manuscript and providing valuable comments. FEBRUARY 2008 PRINTED CIRCUIT DESIGN & FAB 19 http://www.pcbeast.com http://www.pcbeast.com

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Printed Circuit Design & Fab - February 2008

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