Printed Circuit Design & Fab - February 2008 - (Page 20)

IC/PCB CO-DESIGN Improving Circuit Design Using IC Package/PCB CO-DESIGN Techniques Dynamic new co-design strategies will give the PCB designer the flexibility to re-map legacy package pinouts. by MARTIN HART The approach to IC chip packaging design has remained fundamentally unchanged since the 1970s. The chip design team lays out the silicon die and decides what type of IC package to use and how to assign the pinouts. While efforts continue to make co-design of electronic assemblies a reality, no clear communication channel presently exists between the chip and PCB design teams. IC packages are, as the saying goes, simply “tossed over-the-wall” to board designers who are left to deal with whatever comes their way. This is a condition that might well be called “Chip Packaging 1.0” (FIGURE 1). Since the IC package pinouts are documented in the chipmaker’s datasheet, the board designer has no ability to change any aspect of the IC package or to re-map the pinout when necessary. As a result, the board designer has his shoelaces tied when he enters the race to design his product. In spite of the recent hoopla to bring co-design into the mainstream, the long-standing protocol of IC design may never entirely go away. However, improvements are possible if IC packaging adopts a new approach that offers more design freedom in what might be codified as the “Chip Packaging 2.0” environment. This new approach is compelling and worthy of consideration. In the new approach, the PCB designer will use their EDA software to iterate the IC package pinouts of a legacy IC die while simultaneously optimizing the board’s routing (FIGURE 2). This new approach to semiconductor packaging is descriptively referred to as “User Definable Pinout” (UDPo), which enables designers to re-map package pinouts of legacy chips using EDA soft- ware tools. The optimized chip is wired by the chipmaker according to the pinout instructions of the PCB designer and added to the PCB BOM for assembly using normal SMT assembly practices. In looking at a circuit board’s initial design process, the board designer typically makes a series of tradeoffs between electrical, thermal and mechanical needs. Once component locations are established, the circuit schematic is loaded and autorouting of the board commences. The iteration process begins by benchmarking the initials results achieved with “standard pinout” packages. Next, the EDA software begins the pinout iteration process, and pairs of pinouts on selected IC packages are processed while board routing is observed. During the iterative process, improvement is observed as copper routing is shortened, board size is reduced and/or fewer inner layers are FIGURE 1. Chip packaging 1.0. 20 FIGURE 2. User definable pinouts. FEBRUARY 2008 PRINTED CIRCUIT DESIGN & FAB

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - February 2008

Printed Circuit Design & Fab - February 2008 Contents Our Line Market Watch Around the World Happenings ROI Tip Jar Interconnect Strategies IC/PCB Co-Design Modeling Design Tools Optical Interconnect Trade Shows Laminate Materials Off the Shelf Marketplace Ad Index BGA Bulletin

Printed Circuit Design & Fab - February 2008

For optimal viewing of this digital publication, please enable JavaScript and then refresh the page. If you would like to try to load the digital publication without using Flash Player detection, please click here.