Printed Circuit Design & Fab - February 2008 - (Page 22)

FIGURE 5. QFN package using insulated bonding wire and user defined pinout optimization. FIGURE 6. A non optimized pinout. FIGURE 7. A user defined pinout. nies working on EDA chip co-design and optimization software. Some of these tools were demonstrated during the 2007 Design Automation Conference (DAC) in San Diego and the 2007 Semicon West show in San Francisco. Assuming that the aforementioned issues with EDA software are resolved, the next challenge for the UDPo approach is in assembling die that may have cross-over wire bonding. Traditional wire bonding is very neat and orderly, however, in the proposed environment “neat and orderly” may need to be replaced with visually disorderly wires that cross over each other (like the type manufactured by Microbonds X-Wire insulated bonding wire) in order to achieve design objectives (see FIGURE 4). Most wire bonding machines are easily converted to use insulated bonding wire. FIGURE 5 shows an extreme example of insulated bonding wire used in an open cavity QFN package. Industry standard JEDEC IC package outlines such as QFN, QFP, SOIC, BGA, CSP, TSOP are all easily adapted to the concept of UDPo. When using bonding wires, the cumulative thickness of crossing wires cannot exceed the maximum “headroom” of the IC package, which is approximately 10 mils between the upper most wire and the internal ceiling of the plastic IC package. Assuming that typical insulated bonding wire is 1mil in diameter, the maximum number of crossing wires is easily calculable by the designer, while also allowing for the thickness of the die and the lead frame. The Economics of Designing with User Defined Pinouts A very simple circuit design will help to illustrate how this new UDPo approach can improve design. FIGURE 6 illus22 trates the “before” non-optimized board design. U1 and U2 are off-theshelf 8-pin SOIC packages. The copper routing on the PCB from U1-pin 4 to U2-pin 7 crosses the copper routing from U1-pin 5 to U2-pin 8. To prevent short circuits, board designers would typically add a layer with plated vias to complete the design. For comparison, FIGURE 7 illustrates the “after” “optimized” board, with improvements achieved by simply re-mapping the pinouts of U2 without changing the performance of the silicon die. The optimized board has shorter copper routing, less plated vias and fewer layers. The board designer can thus use EDA chip pinout optimization software to simultaneously iterate and re-map U2, while auto-routing copper traces on the board. After completing the iteration process, the EDA software indicated that 2 bonding wires inside U2 should be remapped, using bonding wires from die pad 7 to lead-frame pin 8 and from die pad 8 to lead-frame pin 7. The EDA software then creates a bonding schedule (net list), and the data is presented to IC packaging fabricators to assemble the legacy die (or wafer). The wire-bonding machine employs insulated bonding wire to prevent short circuits with the chip package, and U2 is then sent to the board assembler who uses standard SMT assembly practices to mount components and complete the board assembly. Though the above examples in Figure 6 and Figure 7 are simple ones, the same processes can be applied to complex board designs. It is anticipated that in the early stage of UDPo design, cost per device will be higher due to low volume, non-recurring development and device testing costs. However, it is likely that these higher costs could easily be offset by the lower material costs in PCBs using this design method (smaller boards, fewer inner layers, smaller cabinetry, etc.) as well as the benefits of a faster time to market. Since resultant board designs will become simpler, it is anticipated that there will also be a lowering of costs related to improved yields, reduced testing and rework and lower field failure rates. Summary The UDPo approach to co-design, which begins design at the IC package itself, is a dynamic new technique for printed circuit board designers, allowing them to optimize board-level designs by actually re-mapping pinouts of legacy die. In the current packaging environment, there is no communication channel for chip designers to collaborate with board designers, and it need not be that way in the future. The old “throw it over the wall” approach to IC/PCB design has reached its practical limits. One solution is to give tools to PCB designers that facilitate their ability to re-map legacy package pinouts without changing the performance of the silicon. With this type of tool, PCB designs could be better optimized using IC pinout co-design techniques. Suitable EDA software that can remap legacy chip pinouts while simultaneously optimizing the board, create a requisite chip pinout-bonding schedule, and seamlessly deliver it to wire bonding machines (via the Internet or by conventional means) will be needed to reap the prospective benefits that await. PCD&F MARTIN HART is founder and CEO of Mirror Semiconductor. For more information, contact info@mirrorsemi.com. ACKNOWLEDGEMENTS My gratitude to Joseph Fjelstad for reviewing the manuscript and furnishing excellent feedback. PRINTED CIRCUIT DESIGN & FAB FEBRUARY 2008

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Printed Circuit Design & Fab - February 2008

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