Printed Circuit Design & Fab - February 2008 - (Page 25)

A B C D E F FIGURE 5. TDR measurement data. Different modeling regions can be easily identified: A) SMA connector; B) test card traces; C) high-speed connector and via reflections; D) backplane traces; E) via and the connector at the receiver’s side; F) receiver’s test card region. FIGURE 4. Measurement setup for backplane measurements. The test cards are connected to Module 6 Slots 7 and 10. The Tx trace is K&L6 and Rx trace is E&F6. An S-parameter simulation is performed on the entire channel at 0 to 10 GHz. In FIGURE 3, the resultant S31 (through) of the channel is illustrated and compares this to the measured data. A good correlation can be observed across the entire frequency range. Measurement Methodology Once the prototype is manufactured, its performance must be verified as a part of the overall system, and this can be efficiently done in the SPICE circuit simulation environment. For this purpose, the measurement-based topological modeling methodology is the most feasible candidate. Once the model is generated, a designer can look at the different parts of the circuit model and see how they will affect the final data transmission. In the following subsection, we will briefly describe the measurement-based topological modeling methodology applied for the same gigabit backplane structure. In general, measurement-based modeling strategy follows four major steps: measure, model, verify and simulate. Although the measurements can be done in time or frequency domains (converted to time), the preference is given to the time-domain measurements because they allow for better resolution for the same measurement bandwidth. The modeling is then performed on time domain voltage or impedance data by applying different strategies for various features of the gigabit backplane. For example, relatively short and lossless discontinuities, such as connectors and vias, can be easily modeled using lumped circuit elements or adding short pieces to the ideal transmission lines, whereas long traces can be modeled using a uniform lossy transmission line model. After the model is generated, it is imperative to compare it with the measurements and adjust its components to obtain the best possible correlation. The final step is to simulate different data patterns to see if the interconnect will perform as expected. the channel. The AirMax connector model in MWS is shown in FIGURE 1; the 20 conductors on the inner two columns are simulated, and waveguide ports are set up on both sides of the connectors, resulting in a 40 port simulation. The conductors on the outer two columns are terminated in 50 ohms. A broadband multiple port simulation is best suited for the CST Microwave Studio (CST MWS) time domain solver, which is based on a hexahedral Cartesian mesh and Perfect Boundary Approximation (PBA) technique. The resultant Touchstone file has been verified against empirical data to ensure the model accuracy. The modules consist of four layers, and the high-speed signals are located on the top and bottom layers. The highspeed traces are 12 mils wide and 1.8 in. long, with a characteristic impedance of 50 ohms. The dielectric material on the modules is N4000-6 (FR4), with electrical properties of r=4.3 and loss tangent=0.019. The backplane is 20 layers, 230 mils thick. The channel routes are all on stripline layers, and the backplane contains several layers of back drilling to minimize the via stub effect. The channel traces on the backplane are 9 mils wide, and Tx module to Rx module distance is 10 in. The dielectric material on the backplane is N400013, with r=3.9 and loss tangent=0.012. A CST MWS Frequency Domain (FD) simulation is used to simulate the transmission lines on the modules and backplane. The CST MWS FD solver employs a tetrahedral mesh and accurately simulates dielectric high-frequency losses. The EM model results of the members of the link (two modules, two connectors and backplane), are combined in the CST Design Studio tool. Design Studio is a circuit simulator that can extract S-parameters and time domain data of individual concatenated blocks. See FIGURE 2 for a view of the Design Studio schematic for this channel. FEBRUARY 2008 Step 1: Time-Domain Measurements To measure the backplane structure, a Tektronix CSA8200 sampling oscilloscope with the IConnect software from the same company was used. The time domain sampling oscilloscope generates a high-speed time domain step that propagates through the interconnect structure. The reflected and transmitted step response can be converted to the frequency domain to PRINTED CIRCUIT DESIGN & FAB 25

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Printed Circuit Design & Fab - February 2008

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