Printed Circuit Design & Fab - February 2008 - (Page 26)

FIGURE 6. Modeling of SMA (left) and the connector–via reflections region (right) by partitioning the impedance profile of the respective regions. FIGURE 7. Lossy model for test card traces and its correlation in time and frequency domains. FIGURE 8. Lossy model for the backplane traces and its correlation in time and frequency domains. obtain S-parameter data such as return and insertion losses. The measurement setup used in the analysis is shown in FIGURE 4. It consists of the sampling oscilloscope with two high bandwidth (20 GHz) sampling modules connected via SMA cables to the test cards of the backplane. Time domain reflectometry measurements allow viewing of the interconnect characteristics in time. The measured data can be displayed as impedance, reflection coefficient or voltage waveforms. FIGURE 5 shows the result of these time-domain measurements. Different regions of the backplane structure can be easily identified from the time domain measurements by disconnecting the test cards from the measured backplane structure and observing time domain reflections from the opens at different points. When a signal enters the backplane structure, it first sees the discontinuity due to the SMA connector of the test card; this is point A in Figure 5. The SMA connector is then followed by the test card’s trace labeled as the region B in the figure. After that, the signal sees a test-card-to-backplane connector and the via-to-trace discontinuities are labeled as the region C. Then the signal propagates through differential traces of the backplane structure (region D) finally approaching the receiver’s test card side, where regions E and F indicate the via-connector and test-card traces, respectively. FIGURE 9. Top: a composite model assembly for the backplane structure; each box corresponds to a different HSPICE subcircuit. Bottom: HSPICE simulation results from composite model assembly compared with TDR measurements. The generated model accurately represents both reflections and losses. into the different regions and ideal transmission lines are assigned for each region. The test card and backplane traces are relatively long structures that exhibit lossy behavior and have to be modeled with lossy transmission lines. FIGURE 7 and FIGURE 8 show the lossy models (and their correlation with the measurements) created for the test card and backplane traces respectively. Note that the test card model was obtained from TDR data only, while the backplane’s losses were obtained from TDR and TDT measurement data. Step 3: Verification of Model’s Performance When individual components for the backplane model assembly are generated, an engineer can assemble the model and verify its performance with the measurements when the same step is applied to the generated model. When all modeling pieces that correspond to reflections and losses for the channel are assembled together, each of the individual components can be fine tuned to archive the desired accuracy in terms of reflected and transmitted data. The general model topology and time domain correlation are shown in FIGURE 9. Step 2: Modeling of Reflections and Losses After identifying the different regions, a designer can start performing modeling. The reflections from the SMAs, highspeed connectors and vias can be modeled using lumped elements or pieces of ideal transmission lines, while the traces have to be modeled with lossy transmission lines. The next figures illustrate the general modeling procedure to model the backplane structure shown in Figure 1. FIGURE 6 shows the impedance profile-based modeling of the reflections from the SMA and high-speed connector regions. To model the structure, the impedance profile is simply subdivided 26 Step 4: Simulation of Data Transmission Once an accurate model is generated, it can be used to predict real signal propagation through the interconnect structure. Different data patterns can be easily synthesized with the software and their response can be plotted in a form of an eye diagram. FIGURE 10 shows the channel model’s FEBRUARY 2008 PRINTED CIRCUIT DESIGN & FAB

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Printed Circuit Design & Fab - February 2008

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