Printed Circuit Design & Fab - February 2008 - (Page 31)

DESIGN TOOLS specific rule. FIGURE 7 shows a coupling violation that could cause excessive crosstalk. Note that the coupled segment is highlighted, and a bounding box encloses the violation. Conclusion In general, design rule checkers can be used for a wide variety of PCB constraints such as impedance control, impedance discontinuities, loss, reflections, termination, traces crossing splits2, etc. Dr. Eric Bogatin describes over one hundred general design guidelines to minimize signal integrity problems3. Typical high speed PCBs have many constraints and very dense routing, and it is likely that not all the design rules will be met. It is then up to the engineer to see if the violations require redesign. Rapid identification and the viewing of any violations allow this decision to be made quickly. No one tool that can do everything. In the SI analysis of PCBs, different tools of varying complexity can be used: for example, a field solver, complex full wave analysis, transmission line simulation, etc. Each tool has its own function and value. Post route design rule checkers offer easy to use, configurable, and quick verification of PCB design, ensuring that design guidelines determined by a time-consuming simulation analysis have been followed. PCD&F GUY DE BURGH is a signal integrity and EMC consultant; gdeburgh@ieee.org. Gene Garat is in sales with MossBay EDA; gene@mossbayeda.com. FIGURE 7. Rule checker can highlight coupling violation. Visit us on the web www.cadpartsusa.com (877) 247-2237 FIGURE 6. Rule checker determines match length on differential nets. EMSAT EMC rule checker, configured as an SI rule checker. FIGURE 3 shows the SI design rules on the left side, with the options used to configure a critical net. Since this rule can vary between internal and external layers, there are two user definable “distance to the edge of the plane” thresholds. Note that the rules can be turned on individually. The rules using a green bullet will be run. Next, the critical nets are identified (FIGURE 4). That’s it – run the check. If there are any violations, both a text report and a graphical view are generated. FIGURE 5 shows one such violation. The offending net is highlighted, showing a segment that is too close to the edge of the plane. One of the great features of a rule checker is that it eliminates human error. Consider trying to match the lengths of these two differential nets manually (FIGURE 6). Differential routing is prevalent in today’s designs, and one of the major concerns in DDR design is the relative skew between the nets in the bus. SI simulation is performed to generate physical rules for the router. The nets are then routed to ensure that net lengths are within a specified tolerance of each other. To verify that the design meets the requirements, simply let the design rule determine that these two traces differ in length by 235 mils, which may or may not be acceptable for design requirements. Such a requirement can be entered as a threshold, and the output of the rule checker displays this information as a simple pass/fail. Should there be any violations, a design rule checker allows viewing of the violation location by quickly zooming in and highlighting the net/trace/via/component that violated the FEBRUARY 2008 The leader in PCB Design and Rapid Prototypes Introduces “The CAD Library Triple Play” SM Schematic Symbols Land Patterns 3D Models See our web site for details. Authorized Reseller for: Simplified Solutions Inc. Symbol Modelers Land Pattern Wizards 3D Footprint Models For the month of January receive a 10% discount off software and services. Use Code #CADP0108 PRINTED CIRCUIT DESIGN & FAB 31 http://www.cadpartsusa.com http://www.cadpartsusa.com

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Printed Circuit Design & Fab - February 2008

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