Printed Circuit Design & Fab - February 2008 - (Page 48)

BGA Size Matters Next generation ASIC and FPGA packages with 0.8-mm pitch and over 2,000 pins will require the use of HDI to accomplish BGA routing. THIS IS THE second in a series of articles on BGA routing methods. My goal is to highlight routing problems associated with large pin-count CHARLES BGAs, and provide PFEIL the PCB designer with effective techniques that enable higher route density and reduction of layer count. The good news is that BGA technology enables high pin-count FPGAs, ASICs and connectors packaged with a very high density array of pins. The bad news is that finer pin-pitches and increased pin-counts are making these devices increasingly difficult to route. The requirement to miniaturize while increasing functionality is the most significant constant driving change in our industry. Fortunately, it keeps skilled PCB designers (and former designers like me working for software vendors) employed! for various FPGA and ASIC packages are listed. Note: Even though I was able to find a data sheet for the highest pincount packages, I am not certain if they are actually in production. If anyone can provide information for actual devices with very high pin-counts, I will add them to this chart in a future article. Impact on Routing, Performance and Cost Since the pin-counts on 0.8-mm pitch BGAs are still reasonably low, the routing task is not too difficult. However there are still some design requirements to be considered: ■ Differential pairs. Unless the design rules in the device area are very small, or innovative via patterns are used (to be described in a later article) then the diff pairs must be split. Since these packages are still quite small, the split distance may not affect signal integrity. You also need to determine if the impedance discontinuity could have an impact. For 1-mm pitch BGAs, I consider a pin-count over 1,500 to be the first threshold for routing difficulty. In the context of laminated FR-4 boards with through-vias, these are some of the potential problems: ■ Layer count. The large number of pins could require additional layers simply to breakout the device. If you have multiple uses of BGAs with more than 1,500 pins, then the route density will require more routing layers. Layer counts over 28 need thinner FR-4 dielectrics and de-lamination can occur at lead-free assembly temperatures. ■ Via aspect ratio. Maintaining high fabrication yields and long-term reliability requires the via length-tohole size ratio to be less than 10:1, preferably 8:1. Boards with over 28 layers make it difficult to keep the through-via size small enough to allow effective routing. As the via pad size increases, it is more likely that diff pairs will have to be split during the breakout as well. ■ The “Catch 22” of circular dependencies. High pin-counts dictate additional layers to route, additional layers require a larger via hole and pad size, and larger vias then reduce routing space forcing additional layers. Once Continued on p. 39 TABLE 1. High pin counts by manufacturer. COMPANY 0.5 mm-pitch Amkor Actel 0.8 mm-pitch Quicklogic Altera 1 mm-pitch Actel Cypress Semi eASIC Intel AMI Semi Lattice Semi Xilinx Altera NEC Fujitsu Toshiba FBGA 1152 51-85179 1152-FCBGA MCH 1704 FFBGA 1704 fcBGA FF1760 DS-1760FBGA FCBGA 1849 FC_BGA PBGA[FC] GTM (N2377) 1152 1152 1152 1300 1704 1704 1760 1760 1849 2116 2304 2377 PT-280 DS-484UBGA05 280 484 fcCSP CS281 180 281 PACKAGE PINS High Pin Counts The current crop of BGAs with less than a 1-mm pitch are not yet pushing high pin-count and as such they can be fairly easily routed. Very high pin-counts can be found in currently used 1-mm pitch packages, and this pitch will be decreasing to 0.8 mm in the coming years. In TABLE 1, the highest pin-counts FIGURE 1. Effective fanout pattern. 48 FIGURE 2. Intel MCH package. TI PRINTED CIRCUIT DESIGN & FAB FEBRUARY 2008

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Printed Circuit Design & Fab - February 2008

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