Printed Circuit Design & Fab - March 2008 - (Page 16)

EMI/EMC and SI Effects from Ground-Return Vias on PCBs At higher frequencies signal loss and noise is reduced when ground-return vias are placed close to the signal vias. THERE IS OFTEN a lively discussion when it comes to the importance of “ground” or ground-return vias for high-speed signals that travel from layer to layer in a PCB. Many claim that there are many ground vias that stitch together the various ground layers, so there is little concern about their exact location. Others will insist that the DR. BRUCE ground-return vias are important to both ARCHAMBEAULT EMI/EMC and SI performance for highspeed signals. The real truth lies somewhere in the middle. It depends on the data rate of the signals, and the amount of signal loss and/or noise generated between the planes. The basic issue is that when a signal travels from one reference plane to another, it may travel through a pair or more of board layers. The return current must also travel from one plane to another. If a nearby metal conductor (ground-return via) is provided, the current will spread out between the planes, using the natural displacement current of the capacitance between the planes. The distance the current will spread is determined by the board’s operating frequency, its dielectric thickness, and the amount of inductance associate with the return current path. Current will always take the path of least impedance. This means the distance the current will spread depends on the impedance caused by the loop inductance of the path created by the signal via and the current return path. This spreading distance becomes very small at high frequencies (> 1 GHz) and any benefit from a ground-return via will only be realized if the ground return via is close to the original signal via. Single Plane Pair Transition We can start by examining the signal loss seen by a high speed signal traveling through a single plane pair, changing reference planes from one plane to the other. FIGURE 1 shows several configurations for the planes and potential ground-return vias. Figure 1a shows a signal via and a ground-return via connected to both ground planes. Figure 1b shows the configuration if one plane is ground and another plane is a power (or other) layer. Only one plane is connected to the potential return via in this configuration. 0.0 GND via S21 Loss (db) -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 No return via Return via connected to one plane Return via unconnected to either plane Signal via PWR via Other signal via -1.6 1.0E+08 1.0E+09 1.0E+10 Frequency (Hz) 1.0E+11 FIGURE 1. Potential return via configurations. 1.0 0.0 -1.0 Loss (dB) -2.0 -3.0 -4.0 -5.0 -6.0 -7.0 -8.0 1.0E+08 No Return Via 50 mils 100 mils 200 mils 400 mils 1.0E+09 1.0E+10 Frequency (Hz) 1.0E+11 FIGURE 3. Signal loss through signal plane pair transition with non ground-return vias. 0.0 -2.0 -4.0 -6.0 Loss (dB) -8.0 -10.0 -12.0 -14.0 -16.0 -18.0 -20.0 1.0E+08 3 layers 4 layers 5 layers 6 layers 7 layers 8 layers 9 layers 10 layers 11 layers 1.0E+09 1.0E+10 Frequency (Hz) 1.0E+11 FIGURE 2. Signal loss through signal plane pair transition. 16 FIGURE 4. Signal loss though multiple plane pair transitions. MARCH 2008 PRINTED CIRCUIT DESIGN & FAB

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Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - March 2008

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