Printed Circuit Design & Fab - March 2008 - (Page 17) 0.0 -2.0 -4.0 -6.0 -8.0 -10.0 -12.0 No Return Via -14.0 Return Via @ 50mils Return Via @ 100mils -16.0 Return Via @ 200mils -18.0 Return Via @ 400mils -20.0 1.0E+08 1.0E+09 1.0E+10 Frequency (Hz) 0.0 S21 Transfer function (dB) -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 1.0E+08 GND via at 50 mils GND via at 100 mils No Return Via Loss (dB) 1.0E+11 1.0E+09 1.0E+10 Frequency (MHz) 1.0E+11 FIGURE 5. Impact of ground return via with no via stub. 0.0 -2.0 -4.0 -6.0 -8.0 -10.0 -12.0 -14.0 Long Via Stub – No Return Via Long Via Stub – Return Via @ 50 mils -16.0 Return Via @ 100mils -18.0 Return Via @ 200mils Return Via @ 400mils -20.0 1.0E+08 1.0E+09 1.0E+10 Frequency (Hz) FIGURE 7. EMI noise launched between planes. 1.0E+11 mean a 2-plane pair transition, and so on. As additional planes are added, the signal loss increases, especially at high frequencies. When a ground-return via is placed in close proximity to the signal via, the loss can be improved, even for a greater number of plane-pair transitions. FIGURE 5 shows the impact of a ground-return via when the transition is all the way through a many layered PCB with no via stub. When a large via stub is present, and the signal simply transitions from one layer to the next, the results in FIGURE 6 show that a ground-return via can again help reduce signal loss. Loss (dB) FIGURE 6. Impact of ground return via with long via stub. EMI Effects Another way for via transitions to impact EMI is for noise signals to be launched between planes and coupled onto other vias or connector pins some distance away. Again, the location of a ground-return via can significantly improve (reduce) the amount of this noise launched between planes. FIGURE 7 shows that the impact is greatest between 1 to 10 GHz, and above about 10 GHz the difference was minimal. Using the previous example, at 3 GHz, a ground-return via placed 50 mils from the signal via would reduce the noise injected between the planes by 6 to 7 dB, easily making a pass/fail difference in some systems. Figure 1c shows the configuration when the potential return via is not connected to either plane, or if a second signal via is nearby the original signal via. First, if we examine the loss for the signal, using S21 as a transfer function of signal “in” versus signal “out”, and we move a ground-return via (Figure 1a) to various distances from the signal via, we can see the impact in FIGURE 2. Frequencies below approximately 1 GHz are not impacted by the location of the ground-return via. However, higher frequencies have significant impact on the amount of loss to the signal. If we are using a 2 Gb/s signal, the first harmonic is at 1 GHz, the third harmonic at 3 GHz, etc. Figure 2 shows that the first and third harmonics are not greatly impacted by this return via. However, if a 6 Gb/s signal is used, the first and third harmonics are at 3 GHz and 9 GHz, respectively. Placing a ground-return via only 50 mils from the signal via can improve the 3rd harmonic by more than 1 dB, which can be very significant, especially for long trace lengths where losses, including dielectric loss, can have a major impact to the signal quality. FIGURE 3 shows the impact of removing the groundreturn via while keeping the return via configurations in Figures 1b and 1c. There is no discernable difference between these return vias and having no ground-return via. Clearly, other signal vias and power vias cannot be assumed to provide a return current path for the original signal via. Summary The question of whether a ground return via needs to be placed close to a signal via can be resolved only when the frequencies of interest are known. At lower frequencies, these ground-return vias are not critical, and normal ground-to-ground stitching can be used to provide a suitable return path. However, at higher frequencies, the amount of loss to the intentional signal’s harmonics and the amount of noise injected between the planes (and potentially escaping the system metal enclosure) can be significantly reduced when a ground-return via is placed close to the original signal vias. Return vias that are not connected to both planes will not provide the needed improvement. PCD&F REFERENCES 1. Xin Chang, Bruce Archambeault, Matteo Cocchini, Francesco De Paulis, Vysakh Sivarajan, Yaojiang Zhang, Jun Fan, Samuel Connor, Antonio Orlandi, and Jim Drewniak. ”Return via Connections for Extending Signal Link Path Bandwidth of Via Transitions, accepted ” for publication in EMC Europe Symposium, September 2008. Multiple Plane Transitions Now, lets consider a PCB where there are multiple layers – for example, a backplane PCB. We can perform the simulation again for any number of plane pair transitions. FIGURE 4 shows the signal loss as additional plane pair transitions are added. Three planes MARCH 2008 DR. BRUCE ARCHAMBEAULT is an IBM Distinguished Engineer and IEEE Fellow; barch@us.ibm.com. PRINTED CIRCUIT DESIGN & FAB 17
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover1) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover2) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page 1) Printed Circuit Design & Fab - March 2008 - Contents (Page 2) Printed Circuit Design & Fab - March 2008 - Contents (Page 3) Printed Circuit Design & Fab - March 2008 - Our Line (Page 4) Printed Circuit Design & Fab - March 2008 - Our Line (Page 5) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - March 2008 - Around the World (Page 8) Printed Circuit Design & Fab - March 2008 - Around the World (Page 9) Printed Circuit Design & Fab - March 2008 - Around the World (Page 10) Printed Circuit Design & Fab - March 2008 - Around the World (Page 11) Printed Circuit Design & Fab - March 2008 - Happenings (Page 12) Printed Circuit Design & Fab - March 2008 - Happenings (Page 13) Printed Circuit Design & Fab - March 2008 - ROI (Page 14) Printed Circuit Design & Fab - March 2008 - ROI (Page 15) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 16) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 17) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 18) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 19) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 20) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 21) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 22) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 23) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 24) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 25) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 26) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 27) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 28) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 29) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 30) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 31) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 32) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 33) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 34) Printed Circuit Design & Fab - March 2008 - Ad Index (Page 35) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 36) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 37) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 38) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 39) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 40) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 41) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 42) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 47) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover4)
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