Printed Circuit Design & Fab - March 2008 - (Page 21)

the logical function of the device has been defined, generally as VHDL or Verilog code, but very little effort has been put into defining the physical connection of the FPGA. Next, the FPGA team concerns itself with the most critical signals. Typically, these are all the high-speed signals, including the clocks. These signals are defined and locked during the FPGA synthesis step. The FPGA vendor will then use place-and-route software to assign the remaining logical signals to physical pins, creating a pin map file, which almost always requires several iterations before the pinout is both physically and mechanically optimized. Only then does the PCB design team become involved. Once the pin mapping is complete, the data is transferred to the PCB team, where it is defined by the librarian for use in the PCB design. This transfer by the librarian is almost always done manually and therefore is also a source of possible error. Finally, the PCB designer instantiates the FPGA symbol into the PCB schematic, and it then goes to PCB place and route. Because the PCB design has not been a factor in the system design until now, the need to add extra board layers because of complex pin maps are not uncommon. From here, the design enters the “tweaking” phase mentioned earlier. In this process, the flexibility of the FPGA pinout is often used to optimize the signal integrity and timing of the PCB. In many designs, the need for tweaking has been exacerbated by the good intentions of the FPGA design team. In an effort to involve the PCB design team, the FPGA locks in the I/O pin assignments early in the process, but later finds that the pin assignments result in PCB layouts that can’t meet signal and timing specifications, or that they must change pinouts for other reasons. The result is that the FPGA pinouts must be reconfigured and the PCB re-spun. While it’s clear that the flexibility of the FPGA is a great help in solving many PCB signal and timing issues, this flexibility is not typically used far enough ahead in the process to prevent the issues that require tweaking later in the design process. MARCH 2008 TABLE 1. Number of connections possible for a given number of pins. PINS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 POSSIBLE CONNECTIONS 2 6 24 120 720 5040 40320 362880 3628800 39916800 479001600 6227020800 87178291200 1.30767E+12 2.09228E+13 3.55687E+14 6.40237E+15 Expand your global reach with electronic reprints! Your company took the time to write and submit a great article to Printed Circuit Design & Fab. Following publication, how can your company capitalize on the hard work you put into an article beyond the reach and lifespan of a single monthly issue? The answer: electronic reprints! With an electronic reprint, it’s easy to show your clients, partners and employees that you have been recognized in a well-respected industry magazine. An electronic reprint also serves as an attractive endorsement, adding credibility to your company and its products and services. For only $995 US per article, you’ll receive an electronic reprint (in Adobe Acrobat .PDF fomat) that has the following features: • A cover page with your company’s marketing copy and “as seen in the pages of Printed Circuit Design & Fab” text. • Your article in full color, formatted as it appeared in the print issue. • A back page containing marketing copy that you select or provide. • The right to post and distribute the article – for life! Increasing PCB Yields Two ways to increase PCB yields are well known. Decrease the number of layers, and complete the design of the board with as few iterations as possible, and fabrication yields increase. Other techniques, such as shortening traces and minimizing the number and length of vias, can also increase yields. Longer traces not only require more board space but also increase the risk of crosstalk, noise, and signal coupling that can compromise timing. Vias can become problems due to mechanical stresses and vibration. Certainly, PCB design teams consistently employ the techniques mentioned above, as well as others, to increase the manufacturing yield of PCBs. However, the later the PCB design team enters the FPGA design process, the fewer the number of successful and contributory options there are available. In the worst case, a routable board may not be achievable, or the only viable solution may be to add layers, thereby reducing yields as well as increasing the cost of the PCB. What is needed is to involve the PCB team earlier in the FPGA design, using a tool that can understand both a PCB schematic representation and the FPGA design language. Further, the tool must be able to quickly translate design changes between both domains. To purchase or inquire about electronic reprints today, send an e-mail to: pcdf_reprints@ upmediagroup.com PRINTED CIRCUIT DESIGN & FAB 21

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - March 2008

Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - March 2008

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