Printed Circuit Design & Fab - March 2008 - (Page 22)

FPGA/PCB CO-DESIGN Concurrent Software I/O Designer FIGURE 1 graphically illustrates both the FPGA and PCB design flows. Essentially, this is what has been previously described as a “traditional” design flow. In Figure 1, the center bar represents the co-design software I/O design management tool function previously discussed. This I/O design tool would dynamically manage communications between the two design flows, providing data when required, keeping both design flows up-to-date, and allowing the flexibility of the FPGA to be maximized. Contrasting Figure 1 with the earlier design description, it can be readily seen that the PCB team involvement has been moved to much earlier in the overall design process – all the way back to the initial VHDL/Verilog description. Using an available software tool like this one, the I/O design manager can monitor the FPGA flow and update the PCB with the current data. Beginning with the intial languagebased description schematic derived earlier in the process, from the initial language-based description, the schematic is revised as each definition from the FPGA is learned. This early schematic may have all the pins assigned, or only the critical pins. As electrical and physical constraints are defined, their influence is accounted for in the PCB design, and as pins are assigned in the FPGA flow, they become defined on the PCB design. The benefits of automation in the PCB pin definition process should also not be overlooked. Any manual transcription of data introduces the chance of error. The greater the number of transcription operations, the greater the chance and likelihood of resultant errors. Looking at the values listed in TABLE 1, you can see that each signal (S) has S! (S factorial) number of interface connections. Thus, a two-pin package has two interface connections; a four-pin package has 24, and a 100- pin FPGA has 9 x 10157 connection combinations. Microsoft Excel cannot even calculate the connection possibilities for a common 1000-pin device (see Table 1). Clearly, the potential for error when manually transferring pin-map data is extremely high. Also, the tools are not one-way data transfers, and constraints can be defined on the PCB side that reflect to the FPGA side. And of course, the real beauty of the FPGA is that its design can be altered to optimize external connections. By allowing the PCB design flow to feed back data to the FPGA design process, all aspects of the PCB design can be optimized. Trace lengths are minimized, and the number of layers and therefore the number and length of vias are reduced as well. The Bottom Line Without question, increased pin count and decreased pin pitch on FPGAs will continue. As this trend marches forward, design complexity will dictate that the best way to increase PCB yields in the shortest possible design time is through the cooperative and parallel design of the FPGA and the PCB. Software tools are now available that provide the I/O designer with the tools needed to perform this precise function. As with high pin counts, several variables can contribute to reduce yield, increase design time and negatively affect profit margin. Among these are long design times caused by pin map entry errors and resulting PCB reiteration, longer-than-necessary traces that affect timing and signal integrity, and unnecessary PCB layers and vias that increase manufacturing cost and reduce reliability. In a PCB design integrating an FPGA, quite literally, every signal and pin has a direct and measurable affect on production yield and profit. Incorporating software that helps manage and mitigate the co-design of the FPGA and PCB is imperative to realizing maximum yield potential. PCD&F COWBOY UP! and REGISTER NOW! • Three Days of Targeted Technical Sessions • One Day Table Top Trade Show • Networking Opportunities • FREE Technical Sessions March 4-6, 2008 www.pcbshows.com/austin YAN KILLY is a technical marketing engineer for Mentor Graphics’ system design division; yan_killy@mentor.com. MARCH 2008 22 PRINTED CIRCUIT DESIGN & FAB http://www.pcbshows.com/austin http://www.pcbshows.com/austin

Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - March 2008

Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin

Printed Circuit Design & Fab - March 2008

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