Printed Circuit Design & Fab - March 2008 - (Page 23) OPTICAL INTERCONNECT OPTOELECTRONICS Comes of Age, Part 2 Optical connectivity is sufficiently advanced, has been reduced to practice and is available for many near term applications. by DR. BRUCE L. BOOTH and JACK FISHER Over the last 20 years there have been many process and material technologies used to develop planar polymer waveguides containing films capable of meeting the current and evolving industry requirements. Sorting through the various techniques used to make polymer waveguides, these processes fall into two basic classes, both using photolithographic processes (sometimes with LDI) to define the waveguide. The distinctly different processes for the two classes are: Ridge Technology. Initially, a polymer ridge or trench is constructed through molding, embossing, or etching that has a higher refractive index than the base polymer. See FIGURE 1 for a schematic outlining the generic process steps for ridge and trench polymer waveguide formation. The lower refractive index polymer surrounding the waveguide region creates the specific guiding properties. Different polymer materials Generic Etching, Molding, Embossing Waveguide Creation Ridge Formation 1. Deposit clad layer polymer on Substrate 2. Deposit WG layer on clad 3. Photo image WG region to enable etching removal of 4. Etch remove WG layer 5. Backfill with clad layer polymer have been evaluated depending on whether a ridge or trench is used to form these waveguides. Diffusion Technology. This method includes the formation of a high refractive index waveguide by monomer diffusion into the light-exposed guide forming region with no mechanical or chemical etching contact. See FIGURE 2 for a schematic showing the diffusion technique process. An essential process feature here is the photomask-defined light exposure of a mobile monomer waveguide forming region in a polymer matrix that converts the monomer to a polymer. The process of continued monomer diffusion into the surrounding guide imaged region increases the density. The addition of other laminated monomer/polymer diffusing layers with the typical three-plus layer configuration is completely photopolymerized after diffusion is complete. The essential steps Trench 1. Deposit clad layer polymer on Substrate 2. 3. Photo image WG region to enable etching removal – alternative routes use 4. Backfill WG polymer into GuideLinkTM Waveguide Process – all layers are Monomer + Polymer Formulations pre-coated on Mylar 1. Photo expose – WG layer Diffusion 2. Add Clad layer #1 3. Remove WG layer Mylar add Clad layer #2 4. Interdiffusion of monomer in all 5. Total photo polymerization – to all 6. Remove Mylar 5. Backfill over coat clad polymer 7. Add Robust polymer layers: High Tg Low CTE FIGURE 1. Generic etching, molding, embossing waveguide creation processes. MARCH 2008 FIGURE 2. GuideLink™ waveguide exposure and processing. PRINTED CIRCUIT DESIGN & FAB 23
Table of Contents Feed for the Digital Edition of Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 Contents Our Line Market Watch Around the World Happenings ROI EMC for the Real World Positive Plating FPGA/PCB Co-design Increases Fabrication Yields Optoelectronics Comes of Age, Part 2 Implementation of Buried Capacitance in High-Speed Designs Ad Index Improved Innerlayer Bonding for Sequential Lamination Off the Shelf Marketplace BGA Bulletin Printed Circuit Design & Fab - March 2008 Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover1) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page Cover2) Printed Circuit Design & Fab - March 2008 - Printed Circuit Design & Fab - March 2008 (Page 1) Printed Circuit Design & Fab - March 2008 - Contents (Page 2) Printed Circuit Design & Fab - March 2008 - Contents (Page 3) Printed Circuit Design & Fab - March 2008 - Our Line (Page 4) Printed Circuit Design & Fab - March 2008 - Our Line (Page 5) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 6) Printed Circuit Design & Fab - March 2008 - Market Watch (Page 7) Printed Circuit Design & Fab - March 2008 - Around the World (Page 8) Printed Circuit Design & Fab - March 2008 - Around the World (Page 9) Printed Circuit Design & Fab - March 2008 - Around the World (Page 10) Printed Circuit Design & Fab - March 2008 - Around the World (Page 11) Printed Circuit Design & Fab - March 2008 - Happenings (Page 12) Printed Circuit Design & Fab - March 2008 - Happenings (Page 13) Printed Circuit Design & Fab - March 2008 - ROI (Page 14) Printed Circuit Design & Fab - March 2008 - ROI (Page 15) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 16) Printed Circuit Design & Fab - March 2008 - EMC for the Real World (Page 17) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 18) Printed Circuit Design & Fab - March 2008 - Positive Plating (Page 19) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 20) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 21) Printed Circuit Design & Fab - March 2008 - FPGA/PCB Co-design Increases Fabrication Yields (Page 22) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 23) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 24) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 25) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 26) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 27) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 28) Printed Circuit Design & Fab - March 2008 - Optoelectronics Comes of Age, Part 2 (Page 29) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 30) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 31) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 32) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 33) Printed Circuit Design & Fab - March 2008 - Implementation of Buried Capacitance in High-Speed Designs (Page 34) Printed Circuit Design & Fab - March 2008 - Ad Index (Page 35) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 36) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 37) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 38) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 39) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 40) Printed Circuit Design & Fab - March 2008 - Improved Innerlayer Bonding for Sequential Lamination (Page 41) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 42) Printed Circuit Design & Fab - March 2008 - Off the Shelf (Page 43) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 44) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 45) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 46) Printed Circuit Design & Fab - March 2008 - Marketplace (Page 47) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page 48) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover3) Printed Circuit Design & Fab - March 2008 - BGA Bulletin (Page Cover4)
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